Lines Matching refs:BIT
81 # define PCI_EN_INIT_WR BIT(0)
82 # define PCI_EN_FIFO_WR BIT(1)
83 # define PCI_REMAP_DAC BIT(2)
89 # define STATUS_FBI_BUSY BIT(7)
91 # define EN_CLIPPING BIT(0) /* enable clipping */
92 # define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */
93 # define EN_ALPHA_WRITE BIT(10)
94 # define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */
103 # define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/
104 # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */
105 # define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */
106 # define LFB_INVERT_Y BIT(13) /* invert Y origin (LFB) */
107 # define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */
108 # define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */
116 # define SLOW_PCI_READS BIT(0) /* 2 ws */
117 # define LFB_READ_AHEAD BIT(1)
121 # define DIS_VGA_PASSTHROUGH BIT(0)
122 # define FBI_RESET BIT(1)
123 # define FIFO_RESET BIT(2)
127 # define SLOW_PCI_WRITES BIT(1) /* 1 ws */
128 # define EN_LFB_READ BIT(3)
130 # define VIDEO_RESET BIT(8)
131 # define EN_BLANKING BIT(12)
132 # define EN_DATA_OE BIT(13)
133 # define EN_BLANK_OE BIT(14)
134 # define EN_HVSYNC_OE BIT(15)
135 # define EN_DCLK_OE BIT(16)
137 # define SEL_INPUT_VCLK_SLAVE BIT(17)
141 # define EN_24BPP BIT(22)
146 # define EN_FAST_RAS_READ BIT(5)
147 # define EN_DRAM_OE BIT(6)
148 # define EN_FAST_RD_AHEAD_WR BIT(7)
153 # define EN_RD_AHEAD_FIFO BIT(21)
154 # define EN_DRAM_REFRESH BIT(22)
158 # define DISABLE_TEXTURE BIT(6)
163 # define DAC_READ_CMD BIT(11) /* set read dacreg mode */
166 # define HDOUBLESCAN BIT(20)
167 # define VDOUBLESCAN BIT(21)
168 # define HSYNC_HIGH BIT(23)
169 # define VSYNC_HIGH BIT(24)
170 # define INTERLACE BIT(26)
196 # define LAUNCH_BITBLT BIT(31) /* Launch BitBLT in BltCommand, bltDstXY or bltSize */
208 # define DACREG_CR0_EN_INDEXED BIT(0) /* enable indexec mode */
209 # define DACREG_CR0_8BIT BIT(1) /* set dac to 8 bits/read */
210 # define DACREG_CR0_PWDOWN BIT(3) /* powerdown dac */
215 # define DACREG_CC_CLKA BIT(7) /* clk A controlled by regs */
217 # define DACREG_CC_CLKB BIT(3) /* clk B controlled by regs */
235 # define DACREG_ICS_CMD_PWDOWN BIT(0) /* powerdown dac */
248 # define DACREG_ICS_CLK0 BIT(5)