Lines Matching refs:u8
22 u8 itssi_2g, itssi_5g;
23 u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
28 u8 revision;
29 u8 il0mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11b/g */
30 u8 et0mac[6] __aligned(sizeof(u16)); /* MAC address for Ethernet */
31 u8 et1mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11a */
32 u8 et2mac[6] __aligned(sizeof(u16)); /* MAC address for extra Ethernet */
33 u8 et0phyaddr; /* MII address for enet0 */
34 u8 et1phyaddr; /* MII address for enet1 */
35 u8 et2phyaddr; /* MII address for enet2 */
36 u8 et0mdcport; /* MDIO for enet0 */
37 u8 et1mdcport; /* MDIO for enet1 */
38 u8 et2mdcport; /* MDIO for enet2 */
43 u8 country_code; /* Country Code */
45 u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
46 u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
47 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
48 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
61 u8 gpio0; /* GPIO pin 0 */
62 u8 gpio1; /* GPIO pin 1 */
63 u8 gpio2; /* GPIO pin 2 */
64 u8 gpio3; /* GPIO pin 3 */
65 u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
66 u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
67 u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
68 u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
69 u8 itssi_a; /* Idle TSSI Target for A-PHY */
70 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
71 u8 tri2g; /* 2.4GHz TX isolation */
72 u8 tri5gl; /* 5.2GHz TX isolation */
73 u8 tri5g; /* 5.3GHz TX isolation */
74 u8 tri5gh; /* 5.8GHz TX isolation */
75 u8 txpid2g[4]; /* 2GHz TX power index */
76 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
77 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
78 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
81 u8 rssisav2g; /* 2GHz RSSI params */
82 u8 rssismc2g;
83 u8 rssismf2g;
84 u8 bxa2g; /* 2GHz BX arch */
85 u8 rssisav5g; /* 5GHz RSSI params */
86 u8 rssismc5g;
87 u8 rssismf5g;
88 u8 bxa5g; /* 5GHz BX arch */
114 u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
117 u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
125 u8 opo;
127 u8 rxgainerr2ga[3];
128 u8 rxgainerr5gla[3];
129 u8 rxgainerr5gma[3];
130 u8 rxgainerr5gha[3];
131 u8 rxgainerr5gua[3];
133 u8 noiselvl2ga[3];
134 u8 noiselvl5gla[3];
135 u8 noiselvl5gma[3];
136 u8 noiselvl5gha[3];
137 u8 noiselvl5gua[3];
139 u8 regrev;
140 u8 txchain;
141 u8 rxchain;
142 u8 antswitch;
148 u8 tempthresh;
149 u8 tempoffset;
151 u8 measpower;
152 u8 tempsense_slope;
153 u8 tempcorrx;
154 u8 tempsense_option;
155 u8 freqoffset_corr;
156 u8 iqcal_swp_dis;
157 u8 hw_iqcal_en;
158 u8 elna2g;
159 u8 elna5g;
160 u8 phycal_tempdelta;
161 u8 temps_period;
162 u8 temps_hysteresis;
163 u8 measpower1;
164 u8 measpower2;
165 u8 pcieingress_war;
192 u8 sar2g;
193 u8 sar5g;
207 u8 (*read8)(struct ssb_device *dev, u16 offset);
210 void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
215 size_t count, u16 offset, u8 reg_width);
217 size_t count, u16 offset, u8 reg_width);
277 u8 core_index;
426 u8 mapped_pcmcia_seg;
456 u8 chip_rev;
459 u8 chip_package;
463 u8 nr_devices;
580 static inline u8 ssb_read8(struct ssb_device *dev, u16 offset) in ssb_read8()
592 static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value) in ssb_write8()
606 size_t count, u16 offset, u8 reg_width) in ssb_block_read()
612 size_t count, u16 offset, u8 reg_width) in ssb_block_write()
684 int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);