Lines Matching defs:ssb_sprom
27 struct ssb_sprom { struct
28 u8 revision;
33 u8 et0phyaddr; /* MII address for enet0 */
34 u8 et1phyaddr; /* MII address for enet1 */
35 u8 et2phyaddr; /* MII address for enet2 */
36 u8 et0mdcport; /* MDIO for enet0 */
37 u8 et1mdcport; /* MDIO for enet1 */
38 u8 et2mdcport; /* MDIO for enet2 */
39 u16 dev_id; /* Device ID overriding e.g. PCI ID */
40 u16 board_rev; /* Board revision number from SPROM. */
41 u16 board_num; /* Board number from SPROM. */
42 u16 board_type; /* Board type from SPROM. */
43 u8 country_code; /* Country Code */
44 char alpha2[2]; /* Country Code as two chars like EU or US */
45 u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
46 u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
47 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
48 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
49 u16 pa0b0;
50 u16 pa0b1;
51 u16 pa0b2;
52 u16 pa1b0;
53 u16 pa1b1;
54 u16 pa1b2;
55 u16 pa1lob0;
56 u16 pa1lob1;
57 u16 pa1lob2;
58 u16 pa1hib0;
59 u16 pa1hib1;
60 u16 pa1hib2;
61 u8 gpio0; /* GPIO pin 0 */
62 u8 gpio1; /* GPIO pin 1 */
63 u8 gpio2; /* GPIO pin 2 */
64 u8 gpio3; /* GPIO pin 3 */
65 u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
66 u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
67 u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
68 u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
69 u8 itssi_a; /* Idle TSSI Target for A-PHY */
70 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
71 u8 tri2g; /* 2.4GHz TX isolation */
72 u8 tri5gl; /* 5.2GHz TX isolation */
73 u8 tri5g; /* 5.3GHz TX isolation */
74 u8 tri5gh; /* 5.8GHz TX isolation */
75 u8 txpid2g[4]; /* 2GHz TX power index */
76 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
77 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
78 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
79 s8 rxpo2g; /* 2GHz RX power offset */
103 struct ssb_sprom_core_pwr_info core_pwr_info[4]; argument
108 struct {
110 } antenna_gain;
112 struct {
119 } fem;
121 u16 mcs2gpo[8];
122 u16 mcs5gpo[8];
123 u16 mcs5glpo[8];
124 u16 mcs5ghpo[8];
125 u8 opo;
127 u8 rxgainerr2ga[3];
128 u8 rxgainerr5gla[3];
129 u8 rxgainerr5gma[3];
130 u8 rxgainerr5gha[3];
131 u8 rxgainerr5gua[3];
133 u8 noiselvl2ga[3];
134 u8 noiselvl5gla[3];
135 u8 noiselvl5gma[3];
136 u8 noiselvl5gha[3];
137 u8 noiselvl5gua[3];
139 u8 regrev;
140 u8 txchain;
141 u8 rxchain;
142 u8 antswitch;
143 u16 cddpo;
144 u16 stbcpo;
145 u16 bw40po;
146 u16 bwduppo;
148 u8 tempthresh;
149 u8 tempoffset;
150 u16 rawtempsense;
151 u8 measpower;
152 u8 tempsense_slope;
153 u8 tempcorrx;
154 u8 tempsense_option;
155 u8 freqoffset_corr;
156 u8 iqcal_swp_dis;
157 u8 hw_iqcal_en;
158 u8 elna2g;
159 u8 elna5g;
160 u8 phycal_tempdelta;
161 u8 temps_period;
162 u8 temps_hysteresis;
163 u8 measpower1;
164 u8 measpower2;
165 u8 pcieingress_war;
168 u16 cckbw202gpo;
169 u16 cckbw20ul2gpo;
170 u32 legofdmbw202gpo;
171 u32 legofdmbw20ul2gpo;
172 u32 legofdmbw205glpo;
173 u32 legofdmbw20ul5glpo;
174 u32 legofdmbw205gmpo;
175 u32 legofdmbw20ul5gmpo;
176 u32 legofdmbw205ghpo;
177 u32 legofdmbw20ul5ghpo;
178 u32 mcsbw202gpo;
179 u32 mcsbw20ul2gpo;
180 u32 mcsbw402gpo;
181 u32 mcsbw205glpo;
182 u32 mcsbw20ul5glpo;
183 u32 mcsbw405glpo;
184 u32 mcsbw205gmpo;
185 u32 mcsbw20ul5gmpo;
186 u32 mcsbw405gmpo;
187 u32 mcsbw205ghpo;
188 u32 mcsbw20ul5ghpo;
189 u32 mcsbw405ghpo;
190 u16 mcs32po;
191 u16 legofdm40duppo;
192 u8 sar2g;
193 u8 sar5g;