Lines Matching refs:u32
43 u32 sync_clk;
46 u32 cs_on; /* Assertion time */
47 u32 cs_rd_off; /* Read deassertion time */
48 u32 cs_wr_off; /* Write deassertion time */
51 u32 adv_on; /* Assertion time */
52 u32 adv_rd_off; /* Read deassertion time */
53 u32 adv_wr_off; /* Write deassertion time */
56 u32 we_on; /* WE assertion time */
57 u32 we_off; /* WE deassertion time */
60 u32 oe_on; /* OE assertion time */
61 u32 oe_off; /* OE deassertion time */
64 u32 page_burst_access; /* Multiple access word delay */
65 u32 access; /* Start-cycle to first data valid delay */
66 u32 rd_cycle; /* Total read cycle time */
67 u32 wr_cycle; /* Total write cycle time */
69 u32 bus_turnaround;
70 u32 cycle2cycle_delay;
72 u32 wait_monitoring;
73 u32 clk_activation;
76 u32 wr_access; /* WRACCESSTIME */
77 u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */
84 u32 t_ceasu; /* address setup to CS valid */
85 u32 t_avdasu; /* address setup to ADV valid */
93 u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
94 u32 t_avdp_w;
95 u32 t_aavdh; /* address hold time */
96 u32 t_oeasu; /* address setup to OE valid */
97 u32 t_aa; /* access time from ADV assertion */
98 u32 t_iaa; /* initial access time */
99 u32 t_oe; /* access time from OE assertion */
100 u32 t_ce; /* access time from CS asertion */
101 u32 t_rd_cycle; /* read cycle time */
102 u32 t_cez_r; /* read CS deassertion to high Z */
103 u32 t_cez_w; /* write CS deassertion to high Z */
104 u32 t_oez; /* OE deassertion to high Z */
105 u32 t_weasu; /* address setup to WE valid */
106 u32 t_wpl; /* write assertion time */
107 u32 t_wph; /* write deassertion time */
108 u32 t_wr_cycle; /* write cycle time */
110 u32 clk;
111 u32 t_bacc; /* burst access valid clock to output delay */
112 u32 t_ces; /* CS setup time to clk */
113 u32 t_avds; /* ADV setup time to clk */
114 u32 t_avdh; /* ADV hold time from clk */
115 u32 t_ach; /* address hold time from clk */
116 u32 t_rdyo; /* clk to ready valid */
118 u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
119 u32 t_ce_avd; /* CS on to ADV on delay */
128 u32 cyc_iaa; /* initial access time in cycles */
146 u32 burst_len; /* page/burst length */
147 u32 device_width; /* device bus width (8 or 16 bit) */
148 u32 mux_add_data; /* multiplex address & data */
149 u32 wait_pin; /* wait-pin to be used */
164 extern void gpmc_cs_write_reg(int cs, int idx, u32 val);