Lines Matching defs:gpmc_device_timings
83 struct gpmc_device_timings { struct
84 u32 t_ceasu; /* address setup to CS valid */
85 u32 t_avdasu; /* address setup to ADV valid */
93 u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
94 u32 t_avdp_w;
95 u32 t_aavdh; /* address hold time */
96 u32 t_oeasu; /* address setup to OE valid */
97 u32 t_aa; /* access time from ADV assertion */
98 u32 t_iaa; /* initial access time */
99 u32 t_oe; /* access time from OE assertion */
100 u32 t_ce; /* access time from CS asertion */
101 u32 t_rd_cycle; /* read cycle time */
102 u32 t_cez_r; /* read CS deassertion to high Z */
103 u32 t_cez_w; /* write CS deassertion to high Z */
104 u32 t_oez; /* OE deassertion to high Z */
105 u32 t_weasu; /* address setup to WE valid */
106 u32 t_wpl; /* write assertion time */
107 u32 t_wph; /* write deassertion time */
108 u32 t_wr_cycle; /* write cycle time */
110 u32 clk;
111 u32 t_bacc; /* burst access valid clock to output delay */
112 u32 t_ces; /* CS setup time to clk */
113 u32 t_avds; /* ADV setup time to clk */
114 u32 t_avdh; /* ADV hold time from clk */
115 u32 t_ach; /* address hold time from clk */
116 u32 t_rdyo; /* clk to ready valid */
118 u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
119 u32 t_ce_avd; /* CS on to ADV on delay */
124 u8 cyc_aavdh_oe;/* read address hold time in cycles */
125 u8 cyc_aavdh_we;/* write address hold time in cycles */
126 u8 cyc_oe; /* access time from OE assertion in cycles */
127 u8 cyc_wpl; /* write deassertion time in cycles */
128 u32 cyc_iaa; /* initial access time in cycles */
154 struct gpmc_device_timings *dev_t); argument