Lines Matching defs:mlx4_caps
504 struct mlx4_caps { struct
505 u64 fw_ver;
506 u32 function;
507 int num_ports;
508 int vl_cap[MLX4_MAX_PORTS + 1];
509 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
510 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
511 u64 def_mac[MLX4_MAX_PORTS + 1];
512 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
513 int gid_table_len[MLX4_MAX_PORTS + 1];
514 int pkey_table_len[MLX4_MAX_PORTS + 1];
515 int trans_type[MLX4_MAX_PORTS + 1];
516 int vendor_oui[MLX4_MAX_PORTS + 1];
517 int wavelength[MLX4_MAX_PORTS + 1];
518 u64 trans_code[MLX4_MAX_PORTS + 1];
519 int local_ca_ack_delay;
520 int num_uars;
521 u32 uar_page_size;
522 int bf_reg_size;
523 int bf_regs_per_page;
524 int max_sq_sg;
525 int max_rq_sg;
526 int num_qps;
527 int max_wqes;
528 int max_sq_desc_sz;
529 int max_rq_desc_sz;
530 int max_qp_init_rdma;
531 int max_qp_dest_rdma;
532 u32 *qp0_qkey;
533 u32 *qp0_proxy;
534 u32 *qp1_proxy;
535 u32 *qp0_tunnel;
536 u32 *qp1_tunnel;
537 int num_srqs;
538 int max_srq_wqes;
539 int max_srq_sge;
540 int reserved_srqs;
541 int num_cqs;
542 int max_cqes;
543 int reserved_cqs;
544 int num_sys_eqs;
545 int num_eqs;
546 int reserved_eqs;
547 int num_comp_vectors;
548 int num_mpts;
549 int max_fmr_maps;
550 int num_mtts;
551 int fmr_reserved_mtts;
552 int reserved_mtts;
553 int reserved_mrws;
554 int reserved_uars;
555 int num_mgms;
556 int num_amgms;
557 int reserved_mcgs;
558 int num_qp_per_mgm;
559 int steering_mode;
560 int dmfs_high_steer_mode;
561 int fs_log_max_ucast_qp_range_size;
562 int num_pds;
563 int reserved_pds;
564 int max_xrcds;
565 int reserved_xrcds;
566 int mtt_entry_sz;
567 u32 max_msg_sz;
568 u32 page_size_cap;
569 u64 flags;
570 u64 flags2;
571 u32 bmme_flags;
572 u32 reserved_lkey;
573 u16 stat_rate_support;
574 u8 port_width_cap[MLX4_MAX_PORTS + 1];
575 int max_gso_sz;
576 int max_rss_tbl_sz;
577 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
578 int reserved_qps;
579 int reserved_qps_base[MLX4_NUM_QP_REGION];
580 int log_num_macs;
581 int log_num_vlans;
582 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
583 u8 supported_type[MLX4_MAX_PORTS + 1];
584 u8 suggested_type[MLX4_MAX_PORTS + 1];
585 u8 default_sense[MLX4_MAX_PORTS + 1];
586 u32 port_mask[MLX4_MAX_PORTS + 1];
587 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
588 u32 max_counters;
589 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
590 u16 sqp_demux;
591 u32 eqe_size;
592 u32 cqe_size;
593 u8 eqe_factor;
594 u32 userspace_caps; /* userspace must be aware of these */
595 u32 function_caps; /* VFs must be aware of these */
596 u16 hca_core_clock;
597 u64 phys_port_id[MLX4_MAX_PORTS + 1];
598 int tunnel_offload_mode;
599 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
600 u8 phv_bit[MLX4_MAX_PORTS + 1];
601 u8 alloc_res_qp_mask;
602 u32 dmfs_high_rate_qpn_base;
603 u32 dmfs_high_rate_qpn_range;
604 u32 vf_caps;
605 struct mlx4_rate_limit_caps rl_caps;