Lines Matching defs:intel_iommu
398 struct intel_iommu { struct
399 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
400 u64 reg_phys; /* physical address of hw register set */
401 u64 reg_size; /* size of hw register set */
402 u64 cap;
403 u64 ecap;
404 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
405 raw_spinlock_t register_lock; /* protect register handling */
406 int seq_id; /* sequence id of the iommu */
407 int agaw; /* agaw of this iommu */
408 int msagaw; /* max sagaw of this iommu */
409 unsigned int irq, pr_irq;
410 u16 segment; /* PCI segment# */
411 unsigned char name[13]; /* Device Name */
414 unsigned long *domain_ids; /* bitmap of domains */
415 struct dmar_domain ***domains; /* ptr to domains */
416 spinlock_t lock; /* protect context, domain ids */
417 struct root_entry *root_entry; /* virtual address */
419 struct iommu_flush flush;
447 struct intel_iommu *iommu, void *addr, int size) in __iommu_flush_cache() argument