482 	unsigned int temp_ctl = 0;  in tsi148_slave_set()  local
545 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
547 	temp_ctl &= ~TSI148_LCSR_ITAT_EN;  in tsi148_slave_set()
548 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
566 	temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;  in tsi148_slave_set()
569 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;  in tsi148_slave_set()
572 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;  in tsi148_slave_set()
575 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;  in tsi148_slave_set()
580 	temp_ctl &= ~(0x1F << 7);  in tsi148_slave_set()
582 		temp_ctl |= TSI148_LCSR_ITAT_BLT;  in tsi148_slave_set()
584 		temp_ctl |= TSI148_LCSR_ITAT_MBLT;  in tsi148_slave_set()
586 		temp_ctl |= TSI148_LCSR_ITAT_2eVME;  in tsi148_slave_set()
588 		temp_ctl |= TSI148_LCSR_ITAT_2eSST;  in tsi148_slave_set()
590 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;  in tsi148_slave_set()
593 	temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;  in tsi148_slave_set()
594 	temp_ctl |= addr;  in tsi148_slave_set()
596 	temp_ctl &= ~0xF;  in tsi148_slave_set()
598 		temp_ctl |= TSI148_LCSR_ITAT_SUPR ;  in tsi148_slave_set()
600 		temp_ctl |= TSI148_LCSR_ITAT_NPRIV;  in tsi148_slave_set()
602 		temp_ctl |= TSI148_LCSR_ITAT_PGM;  in tsi148_slave_set()
604 		temp_ctl |= TSI148_LCSR_ITAT_DATA;  in tsi148_slave_set()
607 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
611 		temp_ctl |= TSI148_LCSR_ITAT_EN;  in tsi148_slave_set()
613 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
821 	unsigned int temp_ctl = 0;  in tsi148_master_set()  local
911 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
913 	temp_ctl &= ~TSI148_LCSR_OTAT_EN;  in tsi148_master_set()
914 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
918 	temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;  in tsi148_master_set()
921 		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;  in tsi148_master_set()
924 		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;  in tsi148_master_set()
927 		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;  in tsi148_master_set()
933 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
934 		temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;  in tsi148_master_set()
937 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
938 		temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;  in tsi148_master_set()
941 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
942 		temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;  in tsi148_master_set()
945 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
946 		temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;  in tsi148_master_set()
951 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
952 		temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;  in tsi148_master_set()
956 	temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;  in tsi148_master_set()
959 		temp_ctl |= TSI148_LCSR_OTAT_DBW_16;  in tsi148_master_set()
962 		temp_ctl |= TSI148_LCSR_OTAT_DBW_32;  in tsi148_master_set()
972 	temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;  in tsi148_master_set()
975 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;  in tsi148_master_set()
978 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;  in tsi148_master_set()
981 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;  in tsi148_master_set()
984 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;  in tsi148_master_set()
987 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;  in tsi148_master_set()
990 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;  in tsi148_master_set()
993 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;  in tsi148_master_set()
996 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;  in tsi148_master_set()
999 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;  in tsi148_master_set()
1009 	temp_ctl &= ~(3<<4);  in tsi148_master_set()
1011 		temp_ctl |= TSI148_LCSR_OTAT_SUP;  in tsi148_master_set()
1013 		temp_ctl |= TSI148_LCSR_OTAT_PGM;  in tsi148_master_set()
1030 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1034 		temp_ctl |= TSI148_LCSR_OTAT_EN;  in tsi148_master_set()
1036 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()