Lines Matching refs:dwidth
817 u32 cycle, u32 dwidth) in tsi148_master_set() argument
957 switch (dwidth) { in tsi148_master_set()
1059 u32 *cycle, u32 *dwidth) in __tsi148_master_get() argument
1100 *dwidth = 0; in __tsi148_master_get()
1159 *dwidth = VME_D16; in __tsi148_master_get()
1161 *dwidth = VME_D32; in __tsi148_master_get()
1169 u32 *cycle, u32 *dwidth) in tsi148_master_get() argument
1176 cycle, dwidth); in tsi148_master_get()
1188 u32 aspace, cycle, dwidth; in tsi148_master_read() local
1201 &cycle, &dwidth); in tsi148_master_read()
1274 u32 aspace, cycle, dwidth; in tsi148_master_write() local
1291 &cycle, &dwidth); in tsi148_master_write()
1428 u32 aspace, u32 cycle, u32 dwidth) in tsi148_dma_set_vme_src_attributes() argument
1470 switch (dwidth) { in tsi148_dma_set_vme_src_attributes()
1528 u32 aspace, u32 cycle, u32 dwidth) in tsi148_dma_set_vme_dest_attributes() argument
1570 switch (dwidth) { in tsi148_dma_set_vme_dest_attributes()
1706 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); in tsi148_dma_list_add()
1743 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); in tsi148_dma_list_add()