77 static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,  in tsi148_DMA_irqhandler()  argument
83 		wake_up(&bridge->dma_queue[0]);  in tsi148_DMA_irqhandler()
87 		wake_up(&bridge->dma_queue[1]);  in tsi148_DMA_irqhandler()
97 static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)  in tsi148_LM_irqhandler()  argument
105 			bridge->lm_callback[i](i);  in tsi148_LM_irqhandler()
123 	struct tsi148_driver *bridge;  in tsi148_MB_irqhandler()  local
125 	bridge = tsi148_bridge->driver_priv;  in tsi148_MB_irqhandler()
129 			val = ioread32be(bridge->base +	TSI148_GCSR_MBOX[i]);  in tsi148_MB_irqhandler()
144 	struct tsi148_driver *bridge;  in tsi148_PERR_irqhandler()  local
146 	bridge = tsi148_bridge->driver_priv;  in tsi148_PERR_irqhandler()
150 		ioread32be(bridge->base + TSI148_LCSR_EDPAU),  in tsi148_PERR_irqhandler()
151 		ioread32be(bridge->base + TSI148_LCSR_EDPAL),  in tsi148_PERR_irqhandler()
152 		ioread32be(bridge->base + TSI148_LCSR_EDPAT));  in tsi148_PERR_irqhandler()
156 		ioread32be(bridge->base + TSI148_LCSR_EDPXA),  in tsi148_PERR_irqhandler()
157 		ioread32be(bridge->base + TSI148_LCSR_EDPXS));  in tsi148_PERR_irqhandler()
159 	iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);  in tsi148_PERR_irqhandler()
173 	struct tsi148_driver *bridge;  in tsi148_VERR_irqhandler()  local
175 	bridge = tsi148_bridge->driver_priv;  in tsi148_VERR_irqhandler()
177 	error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);  in tsi148_VERR_irqhandler()
178 	error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);  in tsi148_VERR_irqhandler()
179 	error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);  in tsi148_VERR_irqhandler()
198 	iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);  in tsi148_VERR_irqhandler()
206 static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)  in tsi148_IACK_irqhandler()  argument
208 	wake_up(&bridge->iack_queue);  in tsi148_IACK_irqhandler()
220 	struct tsi148_driver *bridge;  in tsi148_VIRQ_irqhandler()  local
222 	bridge = tsi148_bridge->driver_priv;  in tsi148_VIRQ_irqhandler()
231 			vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);  in tsi148_VIRQ_irqhandler()
250 	struct tsi148_driver *bridge;  in tsi148_irqhandler()  local
254 	bridge = tsi148_bridge->driver_priv;  in tsi148_irqhandler()
257 	enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_irqhandler()
258 	stat = ioread32be(bridge->base + TSI148_LCSR_INTS);  in tsi148_irqhandler()
269 		serviced |= tsi148_DMA_irqhandler(bridge, stat);  in tsi148_irqhandler()
274 		serviced |= tsi148_LM_irqhandler(bridge, stat);  in tsi148_irqhandler()
291 		serviced |= tsi148_IACK_irqhandler(bridge);  in tsi148_irqhandler()
301 	iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);  in tsi148_irqhandler()
311 	struct tsi148_driver *bridge;  in tsi148_irq_init()  local
315 	bridge = tsi148_bridge->driver_priv;  in tsi148_irq_init()
365 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_init()
366 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_init()
374 	struct tsi148_driver *bridge = tsi148_bridge->driver_priv;  in tsi148_irq_exit()  local
377 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_exit()
378 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_exit()
381 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);  in tsi148_irq_exit()
390 static int tsi148_iack_received(struct tsi148_driver *bridge)  in tsi148_iack_received()  argument
394 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);  in tsi148_iack_received()
410 	struct tsi148_driver *bridge;  in tsi148_irq_set()  local
412 	bridge = tsi148_bridge->driver_priv;  in tsi148_irq_set()
416 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
418 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
420 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
422 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
429 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
431 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
433 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
435 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
447 	struct tsi148_driver *bridge;  in tsi148_irq_generate()  local
449 	bridge = tsi148_bridge->driver_priv;  in tsi148_irq_generate()
451 	mutex_lock(&bridge->vme_int);  in tsi148_irq_generate()
454 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
459 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
463 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
466 	wait_event_interruptible(bridge->iack_queue,  in tsi148_irq_generate()
467 		tsi148_iack_received(bridge));  in tsi148_irq_generate()
469 	mutex_unlock(&bridge->vme_int);  in tsi148_irq_generate()
488 	struct tsi148_driver *bridge;  in tsi148_slave_set()  local
491 	bridge = tsi148_bridge->driver_priv;  in tsi148_slave_set()
545 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
548 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
552 	iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
554 	iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
556 	iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
558 	iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
560 	iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
562 	iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
607 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
613 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
631 	struct tsi148_driver *bridge;  in tsi148_slave_get()  local
633 	bridge = image->parent->driver_priv;  in tsi148_slave_get()
638 	ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
641 	vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
643 	vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
645 	vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
647 	vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
649 	pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
651 	pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
827 	struct tsi148_driver *bridge;  in tsi148_master_set()  local
833 	bridge = tsi148_bridge->driver_priv;  in tsi148_master_set()
911 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
914 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1016 	iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1018 	iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1020 	iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1022 	iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1024 	iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1026 	iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1030 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1036 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1067 	struct tsi148_driver *bridge;  in __tsi148_master_get()  local
1069 	bridge = image->parent->driver_priv;  in __tsi148_master_get()
1073 	ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1076 	pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1078 	pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1080 	pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1082 	pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1084 	vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1086 	vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1281 	struct tsi148_driver *bridge;  in tsi148_master_write()  local
1285 	bridge = tsi148_bridge->driver_priv;  in tsi148_master_write()
1350 		ioread16(bridge->flush_image->kern_base + 0x7F000);  in tsi148_master_write()
1379 	struct tsi148_driver *bridge;  in tsi148_master_rmw()  local
1381 	bridge = image->parent->driver_priv;  in tsi148_master_rmw()
1387 	mutex_lock(&bridge->vme_rmw);  in tsi148_master_rmw()
1392 	pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_rmw()
1394 	pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_rmw()
1401 	iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);  in tsi148_master_rmw()
1402 	iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);  in tsi148_master_rmw()
1403 	iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);  in tsi148_master_rmw()
1404 	iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);  in tsi148_master_rmw()
1405 	iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);  in tsi148_master_rmw()
1408 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1410 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1416 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1418 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1422 	mutex_unlock(&bridge->vme_rmw);  in tsi148_master_rmw()
1797 	struct tsi148_driver *bridge;  in tsi148_dma_busy()  local
1799 	bridge = tsi148_bridge->driver_priv;  in tsi148_dma_busy()
1801 	tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +  in tsi148_dma_busy()
1824 	struct tsi148_driver *bridge;  in tsi148_dma_list_exec()  local
1830 	bridge = tsi148_bridge->driver_priv;  in tsi148_dma_list_exec()
1857 	iowrite32be(bus_addr_high, bridge->base +  in tsi148_dma_list_exec()
1859 	iowrite32be(bus_addr_low, bridge->base +  in tsi148_dma_list_exec()
1862 	dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +  in tsi148_dma_list_exec()
1866 	iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +  in tsi148_dma_list_exec()
1869 	retval = wait_event_interruptible(bridge->dma_queue[channel],  in tsi148_dma_list_exec()
1873 		iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base +  in tsi148_dma_list_exec()
1876 		wait_event(bridge->dma_queue[channel],  in tsi148_dma_list_exec()
1886 	val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +  in tsi148_dma_list_exec()
1941 	struct tsi148_driver *bridge;  in tsi148_lm_set()  local
1945 	bridge = tsi148_bridge->driver_priv;  in tsi148_lm_set()
1951 		if (bridge->lm_callback[i] != NULL) {  in tsi148_lm_set()
1990 	iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);  in tsi148_lm_set()
1991 	iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);  in tsi148_lm_set()
1992 	iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_set()
2006 	struct tsi148_driver *bridge;  in tsi148_lm_get()  local
2008 	bridge = lm->parent->driver_priv;  in tsi148_lm_get()
2012 	lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);  in tsi148_lm_get()
2013 	lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);  in tsi148_lm_get()
2014 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_get()
2058 	struct tsi148_driver *bridge;  in tsi148_lm_attach()  local
2062 	bridge = tsi148_bridge->driver_priv;  in tsi148_lm_attach()
2067 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_attach()
2076 	if (bridge->lm_callback[monitor] != NULL) {  in tsi148_lm_attach()
2083 	bridge->lm_callback[monitor] = callback;  in tsi148_lm_attach()
2086 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_attach()
2088 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_attach()
2090 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_attach()
2092 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_attach()
2097 		iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_attach()
2111 	struct tsi148_driver *bridge;  in tsi148_lm_detach()  local
2113 	bridge = lm->parent->driver_priv;  in tsi148_lm_detach()
2118 	lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_detach()
2120 	iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_detach()
2122 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_detach()
2124 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_detach()
2127 		 bridge->base + TSI148_LCSR_INTC);  in tsi148_lm_detach()
2130 	bridge->lm_callback[monitor] = NULL;  in tsi148_lm_detach()
2135 		tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_detach()
2137 		iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_detach()
2151 	struct tsi148_driver *bridge;  in tsi148_slot_get()  local
2153 	bridge = tsi148_bridge->driver_priv;  in tsi148_slot_get()
2156 		slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);  in tsi148_slot_get()
2204 	struct tsi148_driver *bridge;  in tsi148_crcsr_init()  local
2206 	bridge = tsi148_bridge->driver_priv;  in tsi148_crcsr_init()
2209 	bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE,  in tsi148_crcsr_init()
2210 						     &bridge->crcsr_bus);  in tsi148_crcsr_init()
2211 	if (bridge->crcsr_kernel == NULL) {  in tsi148_crcsr_init()
2217 	reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);  in tsi148_crcsr_init()
2219 	iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);  in tsi148_crcsr_init()
2220 	iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);  in tsi148_crcsr_init()
2223 	cbar = ioread32be(bridge->base + TSI148_CBAR);  in tsi148_crcsr_init()
2231 		iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);  in tsi148_crcsr_init()
2235 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_init()
2241 			bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_init()
2249 		retval = tsi148_master_set(bridge->flush_image, 1,  in tsi148_crcsr_init()
2265 	struct tsi148_driver *bridge;  in tsi148_crcsr_exit()  local
2267 	bridge = tsi148_bridge->driver_priv;  in tsi148_crcsr_exit()
2270 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_exit()
2272 		bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_exit()
2275 	iowrite32be(0, bridge->base + TSI148_LCSR_CROU);  in tsi148_crcsr_exit()
2276 	iowrite32be(0, bridge->base + TSI148_LCSR_CROL);  in tsi148_crcsr_exit()
2278 	pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,  in tsi148_crcsr_exit()
2279 		bridge->crcsr_bus);  in tsi148_crcsr_exit()
2598 	struct tsi148_driver *bridge;  in tsi148_remove()  local
2601 	bridge = tsi148_bridge->driver_priv;  in tsi148_remove()
2610 		iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_remove()
2612 		iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_remove()
2619 	iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);  in tsi148_remove()
2624 	iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);  in tsi148_remove()
2629 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);  in tsi148_remove()
2630 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);  in tsi148_remove()
2631 	iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);  in tsi148_remove()
2636 	if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)  in tsi148_remove()
2637 		iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);  in tsi148_remove()
2642 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);  in tsi148_remove()
2643 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);  in tsi148_remove()
2673 	iounmap(bridge->base);  in tsi148_remove()