345 	unsigned int temp_ctl = 0;  in ca91cx42_slave_set()  local
411 	temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
412 	temp_ctl &= ~CA91CX42_VSI_CTL_EN;  in ca91cx42_slave_set()
413 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
421 	temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;  in ca91cx42_slave_set()
422 	temp_ctl |= addr;  in ca91cx42_slave_set()
425 	temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);  in ca91cx42_slave_set()
427 		temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;  in ca91cx42_slave_set()
429 		temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;  in ca91cx42_slave_set()
431 		temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;  in ca91cx42_slave_set()
433 		temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;  in ca91cx42_slave_set()
436 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
439 		temp_ctl |= CA91CX42_VSI_CTL_EN;  in ca91cx42_slave_set()
441 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
604 	unsigned int temp_ctl = 0;  in ca91cx42_master_set()  local
659 	temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
660 	temp_ctl &= ~CA91CX42_LSI_CTL_EN;  in ca91cx42_master_set()
661 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
664 	temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;  in ca91cx42_master_set()
666 		temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;  in ca91cx42_master_set()
668 		temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;  in ca91cx42_master_set()
671 	temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;  in ca91cx42_master_set()
674 		temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;  in ca91cx42_master_set()
677 		temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;  in ca91cx42_master_set()
680 		temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;  in ca91cx42_master_set()
683 		temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;  in ca91cx42_master_set()
694 	temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;  in ca91cx42_master_set()
697 		temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;  in ca91cx42_master_set()
700 		temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;  in ca91cx42_master_set()
703 		temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;  in ca91cx42_master_set()
706 		temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;  in ca91cx42_master_set()
709 		temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;  in ca91cx42_master_set()
712 		temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;  in ca91cx42_master_set()
725 	temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);  in ca91cx42_master_set()
727 		temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;  in ca91cx42_master_set()
729 		temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;  in ca91cx42_master_set()
737 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
740 		temp_ctl |= CA91CX42_LSI_CTL_EN;  in ca91cx42_master_set()
742 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()