1051 	if ((unsigned long)&entry->descriptor & CA91CX42_DCPP_M) {  in ca91cx42_dma_list_add()
1053 			"required: %p\n", &entry->descriptor);  in ca91cx42_dma_list_add()
1058 	memset(&entry->descriptor, 0, sizeof(struct ca91cx42_dma_descriptor));  in ca91cx42_dma_list_add()
1061 		entry->descriptor.dctl |= CA91CX42_DCTL_L2V;  in ca91cx42_dma_list_add()
1098 		entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;  in ca91cx42_dma_list_add()
1103 		entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;  in ca91cx42_dma_list_add()
1106 		entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;  in ca91cx42_dma_list_add()
1109 		entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;  in ca91cx42_dma_list_add()
1112 		entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;  in ca91cx42_dma_list_add()
1122 		entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;  in ca91cx42_dma_list_add()
1125 		entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;  in ca91cx42_dma_list_add()
1128 		entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;  in ca91cx42_dma_list_add()
1131 		entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;  in ca91cx42_dma_list_add()
1134 		entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;  in ca91cx42_dma_list_add()
1143 		entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;  in ca91cx42_dma_list_add()
1145 		entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;  in ca91cx42_dma_list_add()
1147 	entry->descriptor.dtbc = count;  in ca91cx42_dma_list_add()
1148 	entry->descriptor.dla = pci_attr->address;  in ca91cx42_dma_list_add()
1149 	entry->descriptor.dva = vme_attr->address;  in ca91cx42_dma_list_add()
1150 	entry->descriptor.dcpp = CA91CX42_DCPP_NULL;  in ca91cx42_dma_list_add()
1160 		desc_ptr = virt_to_bus(&entry->descriptor);  in ca91cx42_dma_list_add()
1161 		prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;  in ca91cx42_dma_list_add()
1224 	bus_addr = virt_to_bus(&entry->descriptor);  in ca91cx42_dma_list_exec()