Lines Matching refs:ctl
450 unsigned int i, granularity = 0, ctl = 0; in ca91cx42_slave_get() local
464 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_get()
477 if (ctl & CA91CX42_VSI_CTL_EN) in ca91cx42_slave_get()
480 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16) in ca91cx42_slave_get()
482 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24) in ca91cx42_slave_get()
484 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32) in ca91cx42_slave_get()
486 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1) in ca91cx42_slave_get()
488 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2) in ca91cx42_slave_get()
491 if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR) in ca91cx42_slave_get()
493 if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV) in ca91cx42_slave_get()
495 if (ctl & CA91CX42_VSI_CTL_PGM_PGM) in ca91cx42_slave_get()
497 if (ctl & CA91CX42_VSI_CTL_PGM_DATA) in ca91cx42_slave_get()
759 unsigned int i, ctl; in __ca91cx42_master_get() local
767 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); in __ca91cx42_master_get()
781 if (ctl & CA91CX42_LSI_CTL_EN) in __ca91cx42_master_get()
785 switch (ctl & CA91CX42_LSI_CTL_VAS_M) { in __ca91cx42_master_get()
808 if (ctl & CA91CX42_LSI_CTL_VCT_BLT) in __ca91cx42_master_get()
813 if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR) in __ca91cx42_master_get()
818 if (ctl & CA91CX42_LSI_CTL_PGM_PGM) in __ca91cx42_master_get()
824 switch (ctl & CA91CX42_LSI_CTL_VDW_M) { in __ca91cx42_master_get()