Lines Matching refs:bridge
57 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge) in ca91cx42_DMA_irqhandler() argument
59 wake_up(&bridge->dma_queue); in ca91cx42_DMA_irqhandler()
64 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat) in ca91cx42_LM_irqhandler() argument
72 bridge->lm_callback[i](i); in ca91cx42_LM_irqhandler()
81 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask) in ca91cx42_MB_irqhandler() argument
83 wake_up(&bridge->mbox_queue); in ca91cx42_MB_irqhandler()
88 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge) in ca91cx42_IACK_irqhandler() argument
90 wake_up(&bridge->iack_queue); in ca91cx42_IACK_irqhandler()
98 struct ca91cx42_driver *bridge; in ca91cx42_VERR_irqhandler() local
100 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_VERR_irqhandler()
102 val = ioread32(bridge->base + DGCS); in ca91cx42_VERR_irqhandler()
115 struct ca91cx42_driver *bridge; in ca91cx42_LERR_irqhandler() local
117 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_LERR_irqhandler()
119 val = ioread32(bridge->base + DGCS); in ca91cx42_LERR_irqhandler()
133 struct ca91cx42_driver *bridge; in ca91cx42_VIRQ_irqhandler() local
135 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_VIRQ_irqhandler()
140 vec = ioread32(bridge->base + in ca91cx42_VIRQ_irqhandler()
156 struct ca91cx42_driver *bridge; in ca91cx42_irqhandler() local
160 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irqhandler()
162 enable = ioread32(bridge->base + LINT_EN); in ca91cx42_irqhandler()
163 stat = ioread32(bridge->base + LINT_STAT); in ca91cx42_irqhandler()
172 serviced |= ca91cx42_DMA_irqhandler(bridge); in ca91cx42_irqhandler()
175 serviced |= ca91cx42_LM_irqhandler(bridge, stat); in ca91cx42_irqhandler()
177 serviced |= ca91cx42_MB_irqhandler(bridge, stat); in ca91cx42_irqhandler()
179 serviced |= ca91cx42_IACK_irqhandler(bridge); in ca91cx42_irqhandler()
191 iowrite32(serviced, bridge->base + LINT_STAT); in ca91cx42_irqhandler()
200 struct ca91cx42_driver *bridge; in ca91cx42_irq_init() local
202 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irq_init()
212 iowrite32(0, bridge->base + VINT_EN); in ca91cx42_irq_init()
215 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_irq_init()
217 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); in ca91cx42_irq_init()
228 iowrite32(0, bridge->base + LINT_MAP0); in ca91cx42_irq_init()
229 iowrite32(0, bridge->base + LINT_MAP1); in ca91cx42_irq_init()
230 iowrite32(0, bridge->base + LINT_MAP2); in ca91cx42_irq_init()
237 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_irq_init()
242 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge, in ca91cx42_irq_exit() argument
248 iowrite32(0, bridge->base + VINT_EN); in ca91cx42_irq_exit()
251 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_irq_exit()
253 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); in ca91cx42_irq_exit()
255 ca91cx42_bridge = container_of((void *)bridge, struct vme_bridge, in ca91cx42_irq_exit()
260 static int ca91cx42_iack_received(struct ca91cx42_driver *bridge, int level) in ca91cx42_iack_received() argument
264 tmp = ioread32(bridge->base + LINT_STAT); in ca91cx42_iack_received()
281 struct ca91cx42_driver *bridge; in ca91cx42_irq_set() local
283 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irq_set()
286 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_irq_set()
293 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_irq_set()
307 struct ca91cx42_driver *bridge; in ca91cx42_irq_generate() local
309 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irq_generate()
315 mutex_lock(&bridge->vme_int); in ca91cx42_irq_generate()
317 tmp = ioread32(bridge->base + VINT_EN); in ca91cx42_irq_generate()
320 iowrite32(statid << 24, bridge->base + STATID); in ca91cx42_irq_generate()
324 iowrite32(tmp, bridge->base + VINT_EN); in ca91cx42_irq_generate()
327 wait_event_interruptible(bridge->iack_queue, in ca91cx42_irq_generate()
328 ca91cx42_iack_received(bridge, level)); in ca91cx42_irq_generate()
331 tmp = ioread32(bridge->base + VINT_EN); in ca91cx42_irq_generate()
333 iowrite32(tmp, bridge->base + VINT_EN); in ca91cx42_irq_generate()
335 mutex_unlock(&bridge->vme_int); in ca91cx42_irq_generate()
348 struct ca91cx42_driver *bridge; in ca91cx42_slave_set() local
352 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_slave_set()
411 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
413 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
416 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]); in ca91cx42_slave_set()
417 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]); in ca91cx42_slave_set()
418 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]); in ca91cx42_slave_set()
436 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
441 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
452 struct ca91cx42_driver *bridge; in ca91cx42_slave_get() local
454 bridge = image->parent->driver_priv; in ca91cx42_slave_get()
464 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_get()
466 *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]); in ca91cx42_slave_get()
467 vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]); in ca91cx42_slave_get()
468 pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]); in ca91cx42_slave_get()
607 struct ca91cx42_driver *bridge; in ca91cx42_master_set() local
611 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_master_set()
659 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
661 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
732 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]); in ca91cx42_master_set()
733 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]); in ca91cx42_master_set()
734 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]); in ca91cx42_master_set()
737 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
742 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
761 struct ca91cx42_driver *bridge; in __ca91cx42_master_get() local
763 bridge = image->parent->driver_priv; in __ca91cx42_master_get()
767 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); in __ca91cx42_master_get()
769 pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]); in __ca91cx42_master_get()
770 vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]); in __ca91cx42_master_get()
771 pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]); in __ca91cx42_master_get()
979 struct ca91cx42_driver *bridge; in ca91cx42_master_rmw() local
982 bridge = image->parent->driver_priv; in ca91cx42_master_rmw()
989 mutex_lock(&bridge->vme_rmw); in ca91cx42_master_rmw()
1004 iowrite32(0, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1007 iowrite32(mask, bridge->base + SCYC_EN); in ca91cx42_master_rmw()
1008 iowrite32(compare, bridge->base + SCYC_CMP); in ca91cx42_master_rmw()
1009 iowrite32(swap, bridge->base + SCYC_SWP); in ca91cx42_master_rmw()
1010 iowrite32(pci_addr, bridge->base + SCYC_ADDR); in ca91cx42_master_rmw()
1013 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1019 iowrite32(0, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1024 mutex_unlock(&bridge->vme_rmw); in ca91cx42_master_rmw()
1178 struct ca91cx42_driver *bridge; in ca91cx42_dma_busy() local
1180 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_dma_busy()
1182 tmp = ioread32(bridge->base + DGCS); in ca91cx42_dma_busy()
1198 struct ca91cx42_driver *bridge; in ca91cx42_dma_list_exec() local
1202 bridge = ctrlr->parent->driver_priv; in ca91cx42_dma_list_exec()
1228 iowrite32(0, bridge->base + DTBC); in ca91cx42_dma_list_exec()
1229 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP); in ca91cx42_dma_list_exec()
1232 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1241 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1245 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1247 retval = wait_event_interruptible(bridge->dma_queue, in ca91cx42_dma_list_exec()
1251 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1252 iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1254 wait_event(bridge->dma_queue, in ca91cx42_dma_list_exec()
1264 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1270 val = ioread32(bridge->base + DCTL); in ca91cx42_dma_list_exec()
1311 struct ca91cx42_driver *bridge; in ca91cx42_lm_set() local
1314 bridge = lm->parent->driver_priv; in ca91cx42_lm_set()
1329 if (bridge->lm_callback[i] != NULL) { in ca91cx42_lm_set()
1363 iowrite32(lm_base, bridge->base + LM_BS); in ca91cx42_lm_set()
1364 iowrite32(lm_ctl, bridge->base + LM_CTL); in ca91cx42_lm_set()
1378 struct ca91cx42_driver *bridge; in ca91cx42_lm_get() local
1380 bridge = lm->parent->driver_priv; in ca91cx42_lm_get()
1384 *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS); in ca91cx42_lm_get()
1385 lm_ctl = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_get()
1421 struct ca91cx42_driver *bridge; in ca91cx42_lm_attach() local
1424 bridge = lm->parent->driver_priv; in ca91cx42_lm_attach()
1430 lm_ctl = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_attach()
1438 if (bridge->lm_callback[monitor] != NULL) { in ca91cx42_lm_attach()
1445 bridge->lm_callback[monitor] = callback; in ca91cx42_lm_attach()
1448 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_lm_attach()
1450 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_lm_attach()
1455 iowrite32(lm_ctl, bridge->base + LM_CTL); in ca91cx42_lm_attach()
1469 struct ca91cx42_driver *bridge; in ca91cx42_lm_detach() local
1471 bridge = lm->parent->driver_priv; in ca91cx42_lm_detach()
1476 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_lm_detach()
1478 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_lm_detach()
1481 bridge->base + LINT_STAT); in ca91cx42_lm_detach()
1484 bridge->lm_callback[monitor] = NULL; in ca91cx42_lm_detach()
1489 tmp = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_detach()
1491 iowrite32(tmp, bridge->base + LM_CTL); in ca91cx42_lm_detach()
1502 struct ca91cx42_driver *bridge; in ca91cx42_slot_get() local
1504 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_slot_get()
1507 slot = ioread32(bridge->base + VCSR_BS); in ca91cx42_slot_get()
1551 struct ca91cx42_driver *bridge; in ca91cx42_crcsr_init() local
1553 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_crcsr_init()
1559 iowrite32(geoid << 27, bridge->base + VCSR_BS); in ca91cx42_crcsr_init()
1569 bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE, in ca91cx42_crcsr_init()
1570 &bridge->crcsr_bus); in ca91cx42_crcsr_init()
1571 if (bridge->crcsr_kernel == NULL) { in ca91cx42_crcsr_init()
1578 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO); in ca91cx42_crcsr_init()
1580 tmp = ioread32(bridge->base + VCSR_CTL); in ca91cx42_crcsr_init()
1582 iowrite32(tmp, bridge->base + VCSR_CTL); in ca91cx42_crcsr_init()
1591 struct ca91cx42_driver *bridge; in ca91cx42_crcsr_exit() local
1593 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_crcsr_exit()
1596 tmp = ioread32(bridge->base + VCSR_CTL); in ca91cx42_crcsr_exit()
1598 iowrite32(tmp, bridge->base + VCSR_CTL); in ca91cx42_crcsr_exit()
1601 iowrite32(0, bridge->base + VCSR_TO); in ca91cx42_crcsr_exit()
1603 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, in ca91cx42_crcsr_exit()
1604 bridge->crcsr_bus); in ca91cx42_crcsr_exit()
1881 struct ca91cx42_driver *bridge; in ca91cx42_remove() local
1884 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_remove()
1888 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_remove()
1891 iowrite32(0x00800000, bridge->base + LSI0_CTL); in ca91cx42_remove()
1892 iowrite32(0x00800000, bridge->base + LSI1_CTL); in ca91cx42_remove()
1893 iowrite32(0x00800000, bridge->base + LSI2_CTL); in ca91cx42_remove()
1894 iowrite32(0x00800000, bridge->base + LSI3_CTL); in ca91cx42_remove()
1895 iowrite32(0x00800000, bridge->base + LSI4_CTL); in ca91cx42_remove()
1896 iowrite32(0x00800000, bridge->base + LSI5_CTL); in ca91cx42_remove()
1897 iowrite32(0x00800000, bridge->base + LSI6_CTL); in ca91cx42_remove()
1898 iowrite32(0x00800000, bridge->base + LSI7_CTL); in ca91cx42_remove()
1899 iowrite32(0x00F00000, bridge->base + VSI0_CTL); in ca91cx42_remove()
1900 iowrite32(0x00F00000, bridge->base + VSI1_CTL); in ca91cx42_remove()
1901 iowrite32(0x00F00000, bridge->base + VSI2_CTL); in ca91cx42_remove()
1902 iowrite32(0x00F00000, bridge->base + VSI3_CTL); in ca91cx42_remove()
1903 iowrite32(0x00F00000, bridge->base + VSI4_CTL); in ca91cx42_remove()
1904 iowrite32(0x00F00000, bridge->base + VSI5_CTL); in ca91cx42_remove()
1905 iowrite32(0x00F00000, bridge->base + VSI6_CTL); in ca91cx42_remove()
1906 iowrite32(0x00F00000, bridge->base + VSI7_CTL); in ca91cx42_remove()
1941 ca91cx42_irq_exit(bridge, pdev); in ca91cx42_remove()
1943 iounmap(bridge->base); in ca91cx42_remove()