Lines Matching refs:w100_pwr_state
977 static struct power_state w100_pwr_state; variable
1073 w100_pwr_state.pll_cntl.f.pll_pwdn = 0x0; /* power down */ in w100_pll_adjust()
1074 w100_pwr_state.pll_cntl.f.pll_reset = 0x0; /* not reset */ in w100_pll_adjust()
1075 w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x1; /* Hi-Z */ in w100_pll_adjust()
1076 w100_pwr_state.pll_cntl.f.pll_pvg = 0x0; /* VCO gain = 0 */ in w100_pll_adjust()
1077 w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0; /* VCO frequency range control = off */ in w100_pll_adjust()
1078 w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0; /* current offset inside VCO = 0 */ in w100_pll_adjust()
1079 w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0; in w100_pll_adjust()
1087 w100_pwr_state.pll_cntl.f.pll_dactal = 0xd; in w100_pll_adjust()
1088 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); in w100_pll_adjust()
1093 w100_pwr_state.pll_cntl.f.pll_dactal = 0x7; in w100_pll_adjust()
1094 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); in w100_pll_adjust()
1100 if ((w100_pwr_state.pll_cntl.f.pll_vcofr == 0x0) && in w100_pll_adjust()
1101 ((w100_pwr_state.pll_cntl.f.pll_pvg == 0x7) || in w100_pll_adjust()
1102 (w100_pwr_state.pll_cntl.f.pll_ioffset == 0x0))) { in w100_pll_adjust()
1104 w100_pwr_state.pll_cntl.f.pll_vcofr = 0x1; in w100_pll_adjust()
1105 w100_pwr_state.pll_cntl.f.pll_pvg = 0x0; in w100_pll_adjust()
1106 w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0; in w100_pll_adjust()
1110 if ((w100_pwr_state.pll_cntl.f.pll_ioffset) < 0x3) { in w100_pll_adjust()
1111 w100_pwr_state.pll_cntl.f.pll_ioffset += 0x1; in w100_pll_adjust()
1112 } else if ((w100_pwr_state.pll_cntl.f.pll_pvg) < 0x7) { in w100_pll_adjust()
1113 w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0; in w100_pll_adjust()
1114 w100_pwr_state.pll_cntl.f.pll_pvg += 0x1; in w100_pll_adjust()
1133 w100_pwr_state.pll_cntl.f.pll_dactal = 0xa; in w100_pll_calibration()
1134 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); in w100_pll_calibration()
1139 w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0; /* normal */ in w100_pll_calibration()
1140 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); in w100_pll_calibration()
1143 w100_pwr_state.pll_cntl.f.pll_dactal = 0x0; in w100_pll_calibration()
1144 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); in w100_pll_calibration()
1158 if (w100_pwr_state.auto_mode == 1) /* auto mode */ in w100_pll_set_clk()
1160 w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x0; /* disable fast to normal */ in w100_pll_set_clk()
1161 w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x0; /* disable normal to fast */ in w100_pll_set_clk()
1162 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL); in w100_pll_set_clk()
1166 w100_pwr_state.sclk_cntl.f.sclk_src_sel = CLK_SRC_XTAL; in w100_pll_set_clk()
1167 writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL); in w100_pll_set_clk()
1169 w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = pll->M; in w100_pll_set_clk()
1170 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = pll->N_int; in w100_pll_set_clk()
1171 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = pll->N_fac; in w100_pll_set_clk()
1172 w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = pll->lock_time; in w100_pll_set_clk()
1173 writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV); in w100_pll_set_clk()
1175 w100_pwr_state.pwrmgt_cntl.f.pwm_mode_req = 0; in w100_pll_set_clk()
1176 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL); in w100_pll_set_clk()
1180 if (w100_pwr_state.auto_mode == 1) /* auto mode */ in w100_pll_set_clk()
1182 w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x1; /* reenable fast to normal */ in w100_pll_set_clk()
1183 w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x1; /* reenable normal to fast */ in w100_pll_set_clk()
1184 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL); in w100_pll_set_clk()
1207 w100_pwr_state.clk_pin_cntl.f.osc_en = 0x1; in w100_pwm_setup()
1208 w100_pwr_state.clk_pin_cntl.f.osc_gain = 0x1f; in w100_pwm_setup()
1209 w100_pwr_state.clk_pin_cntl.f.dont_use_xtalin = 0x0; in w100_pwm_setup()
1210 w100_pwr_state.clk_pin_cntl.f.xtalin_pm_en = 0x0; in w100_pwm_setup()
1211 w100_pwr_state.clk_pin_cntl.f.xtalin_dbl_en = par->mach->xtal_dbl ? 1 : 0; in w100_pwm_setup()
1212 w100_pwr_state.clk_pin_cntl.f.cg_debug = 0x0; in w100_pwm_setup()
1213 writel((u32) (w100_pwr_state.clk_pin_cntl.val), remapped_regs + mmCLK_PIN_CNTL); in w100_pwm_setup()
1215 w100_pwr_state.sclk_cntl.f.sclk_src_sel = CLK_SRC_XTAL; in w100_pwm_setup()
1216 w100_pwr_state.sclk_cntl.f.sclk_post_div_fast = 0x0; /* Pfast = 1 */ in w100_pwm_setup()
1217 w100_pwr_state.sclk_cntl.f.sclk_clkon_hys = 0x3; in w100_pwm_setup()
1218 w100_pwr_state.sclk_cntl.f.sclk_post_div_slow = 0x0; /* Pslow = 1 */ in w100_pwm_setup()
1219 w100_pwr_state.sclk_cntl.f.disp_cg_ok2switch_en = 0x0; in w100_pwm_setup()
1220 w100_pwr_state.sclk_cntl.f.sclk_force_reg = 0x0; /* Dynamic */ in w100_pwm_setup()
1221 w100_pwr_state.sclk_cntl.f.sclk_force_disp = 0x0; /* Dynamic */ in w100_pwm_setup()
1222 w100_pwr_state.sclk_cntl.f.sclk_force_mc = 0x0; /* Dynamic */ in w100_pwm_setup()
1223 w100_pwr_state.sclk_cntl.f.sclk_force_extmc = 0x0; /* Dynamic */ in w100_pwm_setup()
1224 w100_pwr_state.sclk_cntl.f.sclk_force_cp = 0x0; /* Dynamic */ in w100_pwm_setup()
1225 w100_pwr_state.sclk_cntl.f.sclk_force_e2 = 0x0; /* Dynamic */ in w100_pwm_setup()
1226 w100_pwr_state.sclk_cntl.f.sclk_force_e3 = 0x0; /* Dynamic */ in w100_pwm_setup()
1227 w100_pwr_state.sclk_cntl.f.sclk_force_idct = 0x0; /* Dynamic */ in w100_pwm_setup()
1228 w100_pwr_state.sclk_cntl.f.sclk_force_bist = 0x0; /* Dynamic */ in w100_pwm_setup()
1229 w100_pwr_state.sclk_cntl.f.busy_extend_cp = 0x0; in w100_pwm_setup()
1230 w100_pwr_state.sclk_cntl.f.busy_extend_e2 = 0x0; in w100_pwm_setup()
1231 w100_pwr_state.sclk_cntl.f.busy_extend_e3 = 0x0; in w100_pwm_setup()
1232 w100_pwr_state.sclk_cntl.f.busy_extend_idct = 0x0; in w100_pwm_setup()
1233 writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL); in w100_pwm_setup()
1235 w100_pwr_state.pclk_cntl.f.pclk_src_sel = CLK_SRC_XTAL; in w100_pwm_setup()
1236 w100_pwr_state.pclk_cntl.f.pclk_post_div = 0x1; /* P = 2 */ in w100_pwm_setup()
1237 w100_pwr_state.pclk_cntl.f.pclk_force_disp = 0x0; /* Dynamic */ in w100_pwm_setup()
1238 writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL); in w100_pwm_setup()
1240 w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = 0x0; /* M = 1 */ in w100_pwm_setup()
1241 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = 0x0; /* N = 1.0 */ in w100_pwm_setup()
1242 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = 0x0; in w100_pwm_setup()
1243 w100_pwr_state.pll_ref_fb_div.f.pll_reset_time = 0x5; in w100_pwm_setup()
1244 w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = 0xff; in w100_pwm_setup()
1245 writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV); in w100_pwm_setup()
1247 w100_pwr_state.pll_cntl.f.pll_pwdn = 0x1; in w100_pwm_setup()
1248 w100_pwr_state.pll_cntl.f.pll_reset = 0x1; in w100_pwm_setup()
1249 w100_pwr_state.pll_cntl.f.pll_pm_en = 0x0; in w100_pwm_setup()
1250 w100_pwr_state.pll_cntl.f.pll_mode = 0x0; /* uses VCO clock */ in w100_pwm_setup()
1251 w100_pwr_state.pll_cntl.f.pll_refclk_sel = 0x0; in w100_pwm_setup()
1252 w100_pwr_state.pll_cntl.f.pll_fbclk_sel = 0x0; in w100_pwm_setup()
1253 w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0; in w100_pwm_setup()
1254 w100_pwr_state.pll_cntl.f.pll_pcp = 0x4; in w100_pwm_setup()
1255 w100_pwr_state.pll_cntl.f.pll_pvg = 0x0; in w100_pwm_setup()
1256 w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0; in w100_pwm_setup()
1257 w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0; in w100_pwm_setup()
1258 w100_pwr_state.pll_cntl.f.pll_pecc_mode = 0x0; in w100_pwm_setup()
1259 w100_pwr_state.pll_cntl.f.pll_pecc_scon = 0x0; in w100_pwm_setup()
1260 w100_pwr_state.pll_cntl.f.pll_dactal = 0x0; /* Hi-Z */ in w100_pwm_setup()
1261 w100_pwr_state.pll_cntl.f.pll_cp_clip = 0x3; in w100_pwm_setup()
1262 w100_pwr_state.pll_cntl.f.pll_conf = 0x2; in w100_pwm_setup()
1263 w100_pwr_state.pll_cntl.f.pll_mbctrl = 0x2; in w100_pwm_setup()
1264 w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0; in w100_pwm_setup()
1265 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); in w100_pwm_setup()
1267 w100_pwr_state.pwrmgt_cntl.f.pwm_enable = 0x0; in w100_pwm_setup()
1268 w100_pwr_state.pwrmgt_cntl.f.pwm_mode_req = 0x1; /* normal mode (0, 1, 3) */ in w100_pwm_setup()
1269 w100_pwr_state.pwrmgt_cntl.f.pwm_wakeup_cond = 0x0; in w100_pwm_setup()
1270 w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x0; in w100_pwm_setup()
1271 w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x0; in w100_pwm_setup()
1272 w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_cond = 0x1; /* PM4,ENG */ in w100_pwm_setup()
1273 w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_cond = 0x1; /* PM4,ENG */ in w100_pwm_setup()
1274 w100_pwr_state.pwrmgt_cntl.f.pwm_idle_timer = 0xFF; in w100_pwm_setup()
1275 w100_pwr_state.pwrmgt_cntl.f.pwm_busy_timer = 0xFF; in w100_pwm_setup()
1276 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL); in w100_pwm_setup()
1278 w100_pwr_state.auto_mode = 0; /* manual mode */ in w100_pwm_setup()
1292 w100_pwr_state.sclk_cntl.f.sclk_src_sel = mode->sysclk_src; in w100_init_clocks()
1293 w100_pwr_state.sclk_cntl.f.sclk_post_div_fast = mode->sysclk_divider; in w100_init_clocks()
1294 w100_pwr_state.sclk_cntl.f.sclk_post_div_slow = mode->sysclk_divider; in w100_init_clocks()
1295 writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL); in w100_init_clocks()
1496 w100_pwr_state.pclk_cntl.f.pclk_src_sel = par->mode->pixclk_src; in w100_set_dispregs()
1497 w100_pwr_state.pclk_cntl.f.pclk_post_div = divider; in w100_set_dispregs()
1498 writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL); in w100_set_dispregs()
1521 hsync /= (w100_pwr_state.pclk_cntl.f.pclk_post_div + 1); in calc_hsync()