Lines Matching refs:VIASR
25 struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
26 {VIASR, SR15, 0x02, 0x02},
27 {VIASR, SR16, 0xBF, 0x08},
28 {VIASR, SR17, 0xFF, 0x1F},
29 {VIASR, SR18, 0xFF, 0x4E},
30 {VIASR, SR1A, 0xFB, 0x08},
31 {VIASR, SR1E, 0x0F, 0x01},
32 {VIASR, SR2A, 0xFF, 0x00},
58 struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
59 {VIASR, SR15, 0x02, 0x02},
60 {VIASR, SR16, 0xBF, 0x08},
61 {VIASR, SR17, 0xFF, 0x1F},
62 {VIASR, SR18, 0xFF, 0x4E},
63 {VIASR, SR1A, 0xFB, 0x82},
64 {VIASR, SR1B, 0xFF, 0xF0},
65 {VIASR, SR1F, 0xFF, 0x00},
66 {VIASR, SR1E, 0xFF, 0x01},
67 {VIASR, SR22, 0xFF, 0x1F},
68 {VIASR, SR2A, 0x0F, 0x00},
69 {VIASR, SR2E, 0xFF, 0xFF},
70 {VIASR, SR3F, 0xFF, 0xFF},
71 {VIASR, SR40, 0xF7, 0x00},
72 {VIASR, CR30, 0xFF, 0x04},
108 {VIASR, SR10, 0xFF, 0x01}, /* Unlock Register */
109 {VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */
110 {VIASR, SR17, 0xFF, 0x1F}, /* Display FIFO Control */
111 {VIASR, SR18, 0xFF, 0x4E}, /* GFX PREQ threshold */
112 {VIASR, SR1A, 0xFF, 0x0a}, /* GFX PREQ threshold */
113 {VIASR, SR1F, 0xFF, 0x00}, /* Memory Control 0 */
114 {VIASR, SR1B, 0xFF, 0xF0}, /* Power Management Control 0 */
115 {VIASR, SR1E, 0xFF, 0x01}, /* Power Management Control */
116 {VIASR, SR20, 0xFF, 0x00}, /* Sequencer Arbiter Control 0 */
117 {VIASR, SR21, 0xFF, 0x00}, /* Sequencer Arbiter Control 1 */
118 {VIASR, SR22, 0xFF, 0x1F}, /* Display Arbiter Control 1 */
119 {VIASR, SR2A, 0xFF, 0x00}, /* Power Management Control 5 */
120 {VIASR, SR2D, 0xFF, 0xFF}, /* Power Management Control 1 */
121 {VIASR, SR2E, 0xFF, 0xFF}, /* Power Management Control 2 */
145 struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
146 {VIASR, SR15, 0x02, 0x02},
147 {VIASR, SR16, 0xBF, 0x08},
148 {VIASR, SR17, 0xFF, 0x1F},
149 {VIASR, SR18, 0xFF, 0x4E},
150 {VIASR, SR1A, 0xFB, 0x08},
151 {VIASR, SR1B, 0xFF, 0xF0},
152 {VIASR, SR1E, 0xFF, 0x01},
153 {VIASR, SR2A, 0xFF, 0x00},
154 {VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */
181 {VIASR, SR10, 0xFF, 0x01},
182 {VIASR, SR15, 0x02, 0x02},
183 {VIASR, SR16, 0xBF, 0x08},
184 {VIASR, SR17, 0xFF, 0x1F},
185 {VIASR, SR18, 0xFF, 0x4E},
186 {VIASR, SR1A, 0xFB, 0x08},
187 {VIASR, SR1B, 0xFF, 0xF0},
188 {VIASR, SR1E, 0x07, 0x01},
189 {VIASR, SR2A, 0xF0, 0x00},
190 {VIASR, SR58, 0xFF, 0x00},
191 {VIASR, SR59, 0xFF, 0x00},
192 {VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */
214 struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
215 {VIASR, SR2A, 0x0F, 0x00},
216 {VIASR, SR15, 0x02, 0x02},
217 {VIASR, SR16, 0xBF, 0x08},
218 {VIASR, SR17, 0xFF, 0x1F},
219 {VIASR, SR18, 0xFF, 0x4E},
220 {VIASR, SR1A, 0xFB, 0x08},
238 struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C},
239 {VIASR, 0x18, 0xFF, 0x4C}