Lines Matching refs:value
142 u8 value; in set_primary_pll_state() local
146 value = 0x20; in set_primary_pll_state()
149 value = 0x00; in set_primary_pll_state()
155 via_write_reg_mask(VIASR, 0x2D, value, 0x30); in set_primary_pll_state()
160 u8 value; in set_secondary_pll_state() local
164 value = 0x08; in set_secondary_pll_state()
167 value = 0x00; in set_secondary_pll_state()
173 via_write_reg_mask(VIASR, 0x2D, value, 0x0C); in set_secondary_pll_state()
178 u8 value; in set_engine_pll_state() local
182 value = 0x02; in set_engine_pll_state()
185 value = 0x00; in set_engine_pll_state()
191 via_write_reg_mask(VIASR, 0x2D, value, 0x03); in set_engine_pll_state()
196 u8 value; in set_primary_clock_state() local
200 value = 0x20; in set_primary_clock_state()
203 value = 0x00; in set_primary_clock_state()
209 via_write_reg_mask(VIASR, 0x1B, value, 0x30); in set_primary_clock_state()
214 u8 value; in set_secondary_clock_state() local
218 value = 0x80; in set_secondary_clock_state()
221 value = 0x00; in set_secondary_clock_state()
227 via_write_reg_mask(VIASR, 0x1B, value, 0xC0); in set_secondary_clock_state()