481 	viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);  in viafb_lock_crt()
486 	viafb_write_reg_mask(CR11, VIACR, 0, BIT7);  in viafb_unlock_crt()
487 	viafb_write_reg_mask(CR47, VIACR, 0, BIT0);  in viafb_unlock_crt()
683 	viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);  in viafb_set_primary_color_register()
689 	viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);  in viafb_set_secondary_color_register()
960 	viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);  in load_fix_bit_crtc_reg()
962 	viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);  in load_fix_bit_crtc_reg()
964 	viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);  in load_fix_bit_crtc_reg()
972 		viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);  in load_fix_bit_crtc_reg()
975 		viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);  in load_fix_bit_crtc_reg()
1008 			viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);  in viafb_load_reg()
1010 			viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);  in viafb_load_reg()
1682 		viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);  in viafb_init_dac()
1684 		viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);  in viafb_init_dac()
1691 		viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);  in viafb_init_dac()
1695 		viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);  in viafb_init_dac()
1696 		viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);  in viafb_init_dac()
1703 		viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);  in viafb_init_dac()
1711 	viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);  in device_screen_off()
1717 	viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);  in device_screen_on()
1728 		viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);  in set_display_channel()
1732 		viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);  in set_display_channel()
1735 		viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);  in set_display_channel()
1740 			viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);  in set_display_channel()
1743 			viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);  in set_display_channel()
1815 	viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);  in hw_init()
1859 			viafb_write_reg_mask(index, port, value, mask);  in viafb_setmode()
2048 	viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);  in enable_second_display_channel()
2049 	viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);  in enable_second_display_channel()
2050 	viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);  in enable_second_display_channel()
2056 	viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);  in disable_second_display_channel()
2057 	viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);  in disable_second_display_channel()
2058 	viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);  in disable_second_display_channel()
2068 			viafb_write_reg_mask(CR96, VIACR,  in viafb_set_dpa_gfx()
2072 			viafb_write_reg_mask(SR1E, VIASR,  in viafb_set_dpa_gfx()
2074 			viafb_write_reg_mask(SR2A, VIASR,  in viafb_set_dpa_gfx()
2077 			viafb_write_reg_mask(SR1B, VIASR,  in viafb_set_dpa_gfx()
2079 			viafb_write_reg_mask(SR2A, VIASR,  in viafb_set_dpa_gfx()
2087 			viafb_write_reg_mask(CR9B, VIACR,  in viafb_set_dpa_gfx()
2091 			viafb_write_reg_mask(SR65, VIASR,  in viafb_set_dpa_gfx()
2098 			viafb_write_reg_mask(CR97, VIACR,  in viafb_set_dpa_gfx()
2105 			viafb_write_reg_mask(CR99, VIACR,  in viafb_set_dpa_gfx()
2112 			viafb_write_reg_mask(CR97, VIACR,  in viafb_set_dpa_gfx()
2114 			viafb_write_reg_mask(CR99, VIACR,  in viafb_set_dpa_gfx()