59 		viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);  in viafb_tmds_trasmitter_identify()
66 		viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);  in viafb_tmds_trasmitter_identify()
69 		viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);  in viafb_tmds_trasmitter_identify()
75 		viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +  in viafb_tmds_trasmitter_identify()
80 		viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);  in viafb_tmds_trasmitter_identify()
339 	viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);  in dvi_patch_skew_dvp0()
340 	viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);  in dvi_patch_skew_dvp0()
348 				viafb_write_reg_mask(CR96, VIACR, 0x03,  in dvi_patch_skew_dvp0()
351 				viafb_write_reg_mask(CR96, VIACR, 0x07,  in dvi_patch_skew_dvp0()
358 			viafb_write_reg_mask(CR96, VIACR, 0x07,  in dvi_patch_skew_dvp0()
360 			viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);  in dvi_patch_skew_dvp0()
361 			viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);  in dvi_patch_skew_dvp0()
377 			viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);  in dvi_patch_skew_dvp_low()
383 			viafb_write_reg_mask(CR99, VIACR, 0x08,  in dvi_patch_skew_dvp_low()
390 			viafb_write_reg_mask(CR99, VIACR, 0x0F,  in dvi_patch_skew_dvp_low()
409 		viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);  in viafb_dvi_enable()
410 		viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);  in viafb_dvi_enable()
422 			viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);  in viafb_dvi_enable()
434 			viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);  in viafb_dvi_enable()
435 			viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);  in viafb_dvi_enable()
467 		viafb_write_reg_mask(CR91, VIACR, 0, BIT7);  in viafb_dvi_enable()
470 		viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);  in viafb_dvi_enable()
476 		viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);  in viafb_dvi_enable()