58 		sr2a = viafb_read_reg(VIASR, SR2A);  in viafb_tmds_trasmitter_identify()
59 		viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);  in viafb_tmds_trasmitter_identify()
65 		sr2a = viafb_read_reg(VIASR, SR2A);  in viafb_tmds_trasmitter_identify()
66 		viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);  in viafb_tmds_trasmitter_identify()
68 		sr1e = viafb_read_reg(VIASR, SR1E);  in viafb_tmds_trasmitter_identify()
69 		viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);  in viafb_tmds_trasmitter_identify()
74 		sr1e = viafb_read_reg(VIASR, SR1E);  in viafb_tmds_trasmitter_identify()
75 		viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +  in viafb_tmds_trasmitter_identify()
79 		sr3e = viafb_read_reg(VIASR, SR3E);  in viafb_tmds_trasmitter_identify()
80 		viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);  in viafb_tmds_trasmitter_identify()
127 		viafb_write_reg(SR2A, VIASR, sr2a);  in viafb_tmds_trasmitter_identify()
132 		viafb_write_reg(SR2A, VIASR, sr2a);  in viafb_tmds_trasmitter_identify()
133 		viafb_write_reg(SR1E, VIASR, sr1e);  in viafb_tmds_trasmitter_identify()
137 		viafb_write_reg(SR1E, VIASR, sr1e);  in viafb_tmds_trasmitter_identify()
138 		viafb_write_reg(SR3E, VIASR, sr3e);  in viafb_tmds_trasmitter_identify()
203 		RegSR1E = viafb_read_reg(VIASR, SR1E);  in viafb_dvi_sense()
204 		viafb_write_reg(SR1E, VIASR, RegSR1E | 0x30);  in viafb_dvi_sense()
223 		RegSR1E = viafb_read_reg(VIASR, SR1E);  in viafb_dvi_sense()
224 		viafb_write_reg(SR1E, VIASR, RegSR1E | 0xF0);  in viafb_dvi_sense()
228 		RegSR3E = viafb_read_reg(VIASR, SR3E);  in viafb_dvi_sense()
229 		viafb_write_reg(SR3E, VIASR, RegSR3E & (~0x20));  in viafb_dvi_sense()
252 	viafb_write_reg(SR1E, VIASR, RegSR1E);  in viafb_dvi_sense()
258 		viafb_write_reg(SR3E, VIASR, RegSR3E);  in viafb_dvi_sense()
339 	viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);  in dvi_patch_skew_dvp0()
340 	viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);  in dvi_patch_skew_dvp0()
360 			viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);  in dvi_patch_skew_dvp0()
361 			viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);  in dvi_patch_skew_dvp0()