319 		h = abs(par->vbe_modes[i].x_res - xres) +  in uvesafb_vbe_find_mode()
320 		    abs(par->vbe_modes[i].y_res - yres) +  in uvesafb_vbe_find_mode()
321 		    abs(depth - par->vbe_modes[i].depth);  in uvesafb_vbe_find_mode()
330 		if (h < d || (h == d && par->vbe_modes[i].depth > depth)) {  in uvesafb_vbe_find_mode()
338 			par->vbe_modes[match].depth != depth)  in uvesafb_vbe_find_mode()
491 	par->vbe_modes = kzalloc(sizeof(struct vbe_mode_ib) *  in uvesafb_vbe_getmodes()
493 	if (!par->vbe_modes)  in uvesafb_vbe_getmodes()
506 		task->buf = par->vbe_modes + off;  in uvesafb_vbe_getmodes()
736 		mode = &par->vbe_modes[i];  in uvesafb_vbe_getmonspecs()
848 			if (par->vbe_modes[i].mode_id == vbemode) {  in uvesafb_vbe_init_mode()
851 						&par->vbe_modes[modeid]);  in uvesafb_vbe_init_mode()
904 			modeid = par->vbe_modes[0].mode_id;  in uvesafb_vbe_init_mode()
906 					&par->vbe_modes[modeid]);  in uvesafb_vbe_init_mode()
921 	uvesafb_setup_var(&info->var, info, &par->vbe_modes[modeid]);  in uvesafb_vbe_init_mode()
955 	    par->vbe_modes[i].mode_attr & VBE_MODE_VGACOMPAT) {  in uvesafb_setpalette()
1241 		mode = &par->vbe_modes[i];  in uvesafb_set_par()
1397 	mode = &par->vbe_modes[match];  in uvesafb_check_var()
1410 				!(par->vbe_modes[match].mode_attr & 0x100))  in uvesafb_check_var()
1414 				!(par->vbe_modes[match].mode_attr & 0x200))  in uvesafb_check_var()
1464 		h = par->vbe_modes[i].bytes_per_scan_line *  in uvesafb_init_info()
1465 					par->vbe_modes[i].y_res;  in uvesafb_init_info()
1580 			par->vbe_modes[i].x_res, par->vbe_modes[i].y_res,  in uvesafb_show_vbe_modes()
1581 			par->vbe_modes[i].depth, par->vbe_modes[i].mode_id);  in uvesafb_show_vbe_modes()
1587 static DEVICE_ATTR(vbe_modes, S_IRUGO, uvesafb_show_vbe_modes, NULL);
1718 		mode = &par->vbe_modes[i];  in uvesafb_probe()
1787 	kfree(par->vbe_modes);  in uvesafb_probe()
1809 		kfree(par->vbe_modes);  in uvesafb_remove()