163 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)  in t_outb()  function
399 	t_outb(par, x, 0x2125);  in xp_init_accel()
405 	t_outb(par, 3, 0x2126);  in xp_init_accel()
421 				t_outb(par, 0x00, STATUS);  in xp_wait_engine()
437 	t_outb(par, 0x01, OLDCMD);  in xp_fill_rect()
438 	t_outb(par, par->eng_oper, 0x2125);  in xp_fill_rect()
466 	t_outb(par, ROP_S, 0x2127);  in xp_copy_rect()
470 	t_outb(par, 0x01, OLDCMD);  in xp_copy_rect()
572 	t_outb(par, ROP_P, 0x2127);  in tgui_fill_rect()
577 	t_outb(par, 1, OLDCMD);  in tgui_fill_rect()
605 	t_outb(par, ROP_S, 0x2127);  in tgui_copy_rect()
609 	t_outb(par, 1, OLDCMD);  in tgui_copy_rect()
750 	t_outb(par, PCIReg, 0x3D4);  in disable_mmio()
751 	t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);  in disable_mmio()
876 		t_outb(par, lo, 0x43C8);  in set_vclk()
877 		t_outb(par, hi, 0x43C9);  in set_vclk()
1185 		t_outb(par, tmp | 0xC0, VGA_MIS_W);  in tridentfb_set_par()
1195 		t_outb(par, tmp, VGA_MIS_W);  in tridentfb_set_par()
1326 	t_outb(par, 0x20, VGA_ATT_W);		/* enable attr */  in tridentfb_set_par()
1346 	t_outb(par, tmp, VGA_PEL_MSK);  in tridentfb_set_par()
1375 		t_outb(par, 0xFF, VGA_PEL_MSK);  in tridentfb_setcolreg()
1376 		t_outb(par, regno, VGA_PEL_IW);  in tridentfb_setcolreg()
1378 		t_outb(par, red >> 10, VGA_PEL_D);  in tridentfb_setcolreg()
1379 		t_outb(par, green >> 10, VGA_PEL_D);  in tridentfb_setcolreg()
1380 		t_outb(par, blue >> 10, VGA_PEL_D);  in tridentfb_setcolreg()
1410 	t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */  in tridentfb_blank()
1439 	t_outb(par, 4, 0x83C8);  in tridentfb_blank()
1440 	t_outb(par, PMCont, 0x83C6);  in tridentfb_blank()