Lines Matching refs:regval
462 u8 regval; in s3_set_pixclock() local
473 regval = vga_r(par->state.vgabase, VGA_MIS_R); in s3_set_pixclock()
474 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); in s3_set_pixclock()
492 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ in s3_set_pixclock()
493 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
494 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); in s3_set_pixclock()
495 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
1120 u8 regval, cr38, cr39; in s3_pci_probe() local
1191 regval = vga_rcrt(par->state.vgabase, 0x36); in s3_pci_probe()
1196 switch ((regval & 0xE0) >> 5) { in s3_pci_probe()
1210 switch ((regval & 0xC0) >> 6) { in s3_pci_probe()
1219 switch ((regval & 0x60) >> 5) { in s3_pci_probe()
1234 regval = vga_rcrt(par->state.vgabase, 0x37); in s3_pci_probe()
1235 switch ((regval & 0x60) >> 5) { in s3_pci_probe()
1244 info->screen_size = s3_memsizes[regval >> 5] << 10; in s3_pci_probe()
1248 regval = vga_rseq(par->state.vgabase, 0x10); in s3_pci_probe()
1249 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); in s3_pci_probe()
1250 par->mclk_freq = par->mclk_freq >> (regval >> 5); in s3_pci_probe()