291 	writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV);  in set_clock_divider()
301 	x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);  in set_dma_control0()
326 	writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0);  in set_dma_control0()
338 	x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1);  in set_dma_control1()
348 	writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1);  in set_dma_control1()
361 	writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0);  in set_graphics_start()
373 	x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL) & 0x00000001;  in set_dumb_panel_control()
386 	writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL);  in set_dumb_panel_control()
399 	writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL);  in set_dumb_screen_dimensions()
425 	x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL);  in pxa168fb_set_par()
426 	writel(x & ~1, fbi->reg_base + LCD_SPU_DUMB_CTRL);  in pxa168fb_set_par()
432 		fbi->reg_base + LCD_SPU_V_H_ACTIVE);  in pxa168fb_set_par()
449 	x = readl(fbi->reg_base + LCD_CFG_GRA_PITCH);  in pxa168fb_set_par()
451 	writel(x, fbi->reg_base + LCD_CFG_GRA_PITCH);  in pxa168fb_set_par()
453 		fbi->reg_base + LCD_SPU_GRA_HPXL_VLN);  in pxa168fb_set_par()
455 		fbi->reg_base + LCD_SPU_GZM_HPXL_VLN);  in pxa168fb_set_par()
464 			fbi->reg_base + LCD_SPU_H_PORCH);  in pxa168fb_set_par()
466 			fbi->reg_base + LCD_SPU_V_PORCH);  in pxa168fb_set_par()
471 	x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL);  in pxa168fb_set_par()
472 	writel(x | 1, fbi->reg_base + LCD_SPU_DUMB_CTRL);  in pxa168fb_set_par()
511 		writel(val, fbi->reg_base + LCD_SPU_SRAM_WRDAT);  in pxa168fb_setcolreg()
512 		writel(0x8300 | regno, fbi->reg_base + LCD_SPU_SRAM_CTRL);  in pxa168fb_setcolreg()
539 	u32 isr = readl(fbi->reg_base + SPU_IRQ_ISR);  in pxa168fb_handle_irq()
544 			fbi->reg_base + SPU_IRQ_ISR);  in pxa168fb_handle_irq()
671 	fbi->reg_base = devm_ioremap_nocache(&pdev->dev, res->start,  in pxa168fb_probe()
673 	if (fbi->reg_base == NULL) {  in pxa168fb_probe()
722 	writel(0, fbi->reg_base + LCD_SPU_BLANKCOLOR);  in pxa168fb_probe()
723 	writel(mi->io_pin_allocation_mode, fbi->reg_base + SPU_IOPAD_CONTROL);  in pxa168fb_probe()
724 	writel(0, fbi->reg_base + LCD_CFG_GRA_START_ADDR1);  in pxa168fb_probe()
725 	writel(0, fbi->reg_base + LCD_SPU_GRA_OVSA_HPXL_VLN);  in pxa168fb_probe()
726 	writel(0, fbi->reg_base + LCD_SPU_SRAM_PARA0);  in pxa168fb_probe()
728 		fbi->reg_base + LCD_SPU_SRAM_PARA1);  in pxa168fb_probe()
752 	writel(GRA_FRAME_IRQ0_ENA(0x1), fbi->reg_base + SPU_IRQ_ENA);  in pxa168fb_probe()
792 	data = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);  in pxa168fb_remove()
794 	writel(data, fbi->reg_base + LCD_SPU_DMA_CTRL0);  in pxa168fb_remove()
800 	writel(GRA_FRAME_IRQ0_ENA(0x0), fbi->reg_base + SPU_IRQ_ENA);  in pxa168fb_remove()