265 	fb_writel(type, par->mmio_base + 0x108);  in pvr2fb_set_pal_type()
272 	fb_writel(val, par->mmio_base + 0x1000 + (4 * regno));  in pvr2fb_set_pal_entry()
544 	fb_writel(par->disp_start, DISP_DIWADDRL);  in pvr2_update_display()
545 	fb_writel(par->disp_start +  in pvr2_update_display()
564 	fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE);  in pvr2_init_display()
573 	fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width,  in pvr2_init_display()
577 	fb_writel(par->disp_start, DISP_DIWADDRL);  in pvr2_init_display()
578 	fb_writel(par->disp_start +  in pvr2_init_display()
583 	fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ);  in pvr2_init_display()
584 	fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT);  in pvr2_init_display()
585 	fb_writel(0, DISP_BRDRCOLR);  in pvr2_init_display()
588 	fb_writel(par->diwstart_h, DISP_DIWHSTRT);  in pvr2_init_display()
589 	fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT);  in pvr2_init_display()
592 	fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF);  in pvr2_init_display()
595 	fb_writel(((video_output == VO_VGA) << 23) |  in pvr2_init_display()
599 	fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE);  in pvr2_init_display()
600 	fb_writel(bytesperpixel << 2, DISP_PIXDEPTH);  in pvr2_init_display()
604 	fb_writel(0x100 | ((par->is_interlaced /*|4*/) << 4), DISP_SYNCCONF);  in pvr2_init_display()
618 		fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF);  in pvr2_do_blank()
620 		fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF);  in pvr2_do_blank()
656 		fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000,  in pvr2_init_cable()
665 		fb_writel(3 << 8, VOUTC);  in pvr2_init_cable()
667 		fb_writel(1 << 9, VOUTC);  in pvr2_init_cable()
669 		fb_writel(0, VOUTC);  in pvr2_init_cable()