22 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)  in hdmi_wp_dump()  argument
24 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))  in hdmi_wp_dump()
46 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)  in hdmi_wp_get_irqstatus()  argument
48 	return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);  in hdmi_wp_get_irqstatus()
51 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)  in hdmi_wp_set_irqstatus()  argument
53 	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);  in hdmi_wp_set_irqstatus()
55 	hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);  in hdmi_wp_set_irqstatus()
58 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)  in hdmi_wp_set_irqenable()  argument
60 	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);  in hdmi_wp_set_irqenable()
63 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)  in hdmi_wp_clear_irqenable()  argument
65 	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);  in hdmi_wp_clear_irqenable()
69 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)  in hdmi_wp_set_phy_pwr()  argument
72 	if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)  in hdmi_wp_set_phy_pwr()
76 	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);  in hdmi_wp_set_phy_pwr()
79 	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)  in hdmi_wp_set_phy_pwr()
89 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)  in hdmi_wp_set_pll_pwr()  argument
92 	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);  in hdmi_wp_set_pll_pwr()
95 	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)  in hdmi_wp_set_pll_pwr()
104 int hdmi_wp_video_start(struct hdmi_wp_data *wp)  in hdmi_wp_video_start()  argument
106 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);  in hdmi_wp_video_start()
111 void hdmi_wp_video_stop(struct hdmi_wp_data *wp)  in hdmi_wp_video_stop()  argument
115 	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);  in hdmi_wp_video_stop()
117 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);  in hdmi_wp_video_stop()
124 		v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);  in hdmi_wp_video_stop()
132 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,  in hdmi_wp_video_config_format()  argument
137 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,  in hdmi_wp_video_config_format()
142 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);  in hdmi_wp_video_config_format()
145 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,  in hdmi_wp_video_config_interface()  argument
155 	r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);  in hdmi_wp_video_config_interface()
160 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);  in hdmi_wp_video_config_interface()
163 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,  in hdmi_wp_video_config_timing()  argument
174 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);  in hdmi_wp_video_config_timing()
179 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);  in hdmi_wp_video_config_timing()
204 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,  in hdmi_wp_audio_config_format()  argument
211 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);  in hdmi_wp_audio_config_format()
224 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);  in hdmi_wp_audio_config_format()
227 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,  in hdmi_wp_audio_config_dma()  argument
234 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);  in hdmi_wp_audio_config_dma()
237 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);  in hdmi_wp_audio_config_dma()
239 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);  in hdmi_wp_audio_config_dma()
242 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);  in hdmi_wp_audio_config_dma()
245 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)  in hdmi_wp_audio_enable()  argument
247 	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);  in hdmi_wp_audio_enable()
252 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)  in hdmi_wp_audio_core_req_enable()  argument
254 	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);  in hdmi_wp_audio_core_req_enable()
259 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp)  in hdmi_wp_init()  argument
268 	wp->phys_base = res->start;  in hdmi_wp_init()
270 	wp->base = devm_ioremap_resource(&pdev->dev, res);  in hdmi_wp_init()
271 	if (IS_ERR(wp->base)) {  in hdmi_wp_init()
273 		return PTR_ERR(wp->base);  in hdmi_wp_init()
279 phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)  in hdmi_wp_get_audio_dma_addr()  argument
281 	return wp->phys_base + HDMI_WP_AUDIO_DATA;  in hdmi_wp_get_audio_dma_addr()