Lines Matching refs:REG_FLD_MOD
68 #define REG_FLD_MOD(idx, val, start, end) \ macro
295 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_enable()
299 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ in dss_sdi_enable()
311 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); in dss_sdi_enable()
339 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_enable()
353 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_disable()
427 REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ in dss_select_dispc_clk_source()
455 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ in dss_select_dsi_clk_source()
490 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ in dss_select_lcd_clk_source()
626 REG_FLD_MOD(DSS_CONTROL, l, 6, 6); in dss_set_venc_output()
631 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ in dss_set_dac_pwrdn_bgz()
645 REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */ in dss_select_hdmi_venc_clk_source()
685 REG_FLD_MOD(DSS_CONTROL, val, 17, 17); in dss_dpi_select_source_omap4()
711 REG_FLD_MOD(DSS_CONTROL, val, 17, 16); in dss_dpi_select_source_omap5()
1143 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); in dss_bind()
1148 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ in dss_bind()
1149 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ in dss_bind()
1150 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ in dss_bind()