Lines Matching refs:REG_GET
121 #define REG_GET(dsidev, idx, start, end) \ macro
512 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
519 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
1796 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ in dsi_get_line_buf_size()
2292 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); in dsi_vc_is_enabled()
2303 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) in dsi_packet_sent_handler_vp()
2326 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { in dsi_sync_vc_vp()
2353 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) in dsi_packet_sent_handler_l4()
2372 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { in dsi_sync_vc_l4()
2527 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_flush_long_data()
2579 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_flush_receive_data()
2615 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_send_bta()
2867 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_write_common()
2960 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { in dsi_vc_read_rx_fifo()
3143 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { in dsi_enter_ulps()
3161 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ in dsi_enter_ulps()
3166 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ in dsi_enter_ulps()
5443 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); in dsi_bind()