Lines Matching refs:dispc

133 } dispc;  variable
254 __raw_writel(val, dispc.base + idx); in dispc_write_reg()
259 return __raw_readl(dispc.base + idx); in dispc_read_reg()
275 spin_lock_irqsave(&dispc.control_lock, flags); in mgr_fld_write()
280 spin_unlock_irqrestore(&dispc.control_lock, flags); in mgr_fld_write()
284 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
286 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
390 dispc.ctx_valid = true; in dispc_save_context()
401 if (!dispc.ctx_valid) in dispc_restore_context()
523 r = pm_runtime_get_sync(&dispc.pdev->dev); in dispc_runtime_get()
535 r = pm_runtime_put_sync(&dispc.pdev->dev); in dispc_runtime_put()
548 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) in dispc_mgr_get_framedone_irq()
1133 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | in dispc_mgr_set_size()
1134 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); in dispc_mgr_set_size()
1151 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { in dispc_init_fifos()
1154 dispc.fifo_size[fifo] = size; in dispc_init_fifos()
1160 dispc.fifo_assignment[fifo] = fifo; in dispc_init_fifos()
1170 if (dispc.feat->gfx_fifo_workaround) { in dispc_init_fifos()
1182 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; in dispc_init_fifos()
1183 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; in dispc_init_fifos()
1206 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { in dispc_ovl_get_fifo_size()
1207 if (dispc.fifo_assignment[fifo] == plane) in dispc_ovl_get_fifo_size()
1208 size += dispc.fifo_size[fifo]; in dispc_ovl_get_fifo_size()
1247 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && in dispc_ovl_set_fifo_threshold()
2267 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_24xx()
2322 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_34xx()
2417 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, in dispc_ovl_calc_scaling_44xx()
2477 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height, in dispc_ovl_calc_scaling()
2714 if (dispc.feat->last_pixel_inc_missing) in dispc_ovl_setup_common()
3030 return width <= dispc.feat->mgr_width_max && in _dispc_mgr_size_ok()
3031 height <= dispc.feat->mgr_height_max; in _dispc_mgr_size_ok()
3037 if (hsw < 1 || hsw > dispc.feat->sw_max || in _dispc_lcd_timings_ok()
3038 hfp < 1 || hfp > dispc.feat->hp_max || in _dispc_lcd_timings_ok()
3039 hbp < 1 || hbp > dispc.feat->hp_max || in _dispc_lcd_timings_ok()
3040 vsw < 1 || vsw > dispc.feat->sw_max || in _dispc_lcd_timings_ok()
3041 vfp < 0 || vfp > dispc.feat->vp_max || in _dispc_lcd_timings_ok()
3042 vbp < 0 || vbp > dispc.feat->vp_max) in _dispc_lcd_timings_ok()
3051 return pclk <= dispc.feat->max_lcd_pclk ? true : false; in _dispc_mgr_pclk_ok()
3053 return pclk <= dispc.feat->max_tv_pclk ? true : false; in _dispc_mgr_pclk_ok()
3091 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3092 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3093 FLD_VAL(hbp-1, dispc.feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3094 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3095 FLD_VAL(vfp, dispc.feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3096 FLD_VAL(vbp, dispc.feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3168 if (dispc.syscon_pol) { in _dispc_mgr_set_lcd_timings()
3183 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset, in _dispc_mgr_set_lcd_timings()
3242 dispc.core_clk_rate = dispc_fclk_rate() / lck_div; in dispc_mgr_set_lcd_divisor()
3342 return dispc.tv_pclk_rate; in dispc_mgr_pclk_rate()
3348 dispc.tv_pclk_rate = pclk; in dispc_set_tv_pclk()
3353 return dispc.core_clk_rate; in dispc_core_clk_rate()
3617 bool dispc_div_calc(unsigned long dispc, in dispc_div_calc() argument
3643 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul); in dispc_div_calc()
3644 lckd_stop = min(dispc / pck_min, 255ul); in dispc_div_calc()
3647 lck = dispc / lckd; in dispc_div_calc()
3753 dispc.core_clk_rate = dispc_fclk_rate(); in _omap_dispc_initial_config()
3770 if (dispc.feat->mstandby_workaround) in _omap_dispc_initial_config()
3923 dispc.feat = dst; in dispc_init_features()
3930 if (!dispc.is_enabled) in dispc_irq_handler()
3933 return dispc.user_handler(irq, dispc.user_data); in dispc_irq_handler()
3940 if (dispc.user_handler != NULL) in dispc_request_irq()
3943 dispc.user_handler = handler; in dispc_request_irq()
3944 dispc.user_data = dev_id; in dispc_request_irq()
3949 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, in dispc_request_irq()
3950 IRQF_SHARED, "OMAP DISPC", &dispc); in dispc_request_irq()
3952 dispc.user_handler = NULL; in dispc_request_irq()
3953 dispc.user_data = NULL; in dispc_request_irq()
3962 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); in dispc_free_irq()
3964 dispc.user_handler = NULL; in dispc_free_irq()
3965 dispc.user_data = NULL; in dispc_free_irq()
3978 dispc.pdev = pdev; in dispc_bind()
3980 spin_lock_init(&dispc.control_lock); in dispc_bind()
3982 r = dispc_init_features(dispc.pdev); in dispc_bind()
3986 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); in dispc_bind()
3992 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start, in dispc_bind()
3994 if (!dispc.base) { in dispc_bind()
3999 dispc.irq = platform_get_irq(dispc.pdev, 0); in dispc_bind()
4000 if (dispc.irq < 0) { in dispc_bind()
4006 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); in dispc_bind()
4007 if (IS_ERR(dispc.syscon_pol)) { in dispc_bind()
4009 return PTR_ERR(dispc.syscon_pol); in dispc_bind()
4013 &dispc.syscon_pol_offset)) { in dispc_bind()
4070 dispc.is_enabled = false; in dispc_runtime_suspend()
4074 synchronize_irq(dispc.irq); in dispc_runtime_suspend()
4095 dispc.is_enabled = true; in dispc_runtime_resume()