262 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)  in mgr_fld_read()  argument
264 	const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];  in mgr_fld_read()
268 static void mgr_fld_write(enum omap_channel channel,  in mgr_fld_write()  argument
270 	const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];  in mgr_fld_write()
540 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)  in dispc_mgr_get_vsync_irq()  argument
542 	return mgr_desc[channel].vsync_irq;  in dispc_mgr_get_vsync_irq()
546 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)  in dispc_mgr_get_framedone_irq()  argument
548 	if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)  in dispc_mgr_get_framedone_irq()
551 	return mgr_desc[channel].framedone_irq;  in dispc_mgr_get_framedone_irq()
555 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)  in dispc_mgr_get_sync_lost_irq()  argument
557 	return mgr_desc[channel].sync_lost_irq;  in dispc_mgr_get_sync_lost_irq()
566 bool dispc_mgr_go_busy(enum omap_channel channel)  in dispc_mgr_go_busy()  argument
568 	return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;  in dispc_mgr_go_busy()
572 void dispc_mgr_go(enum omap_channel channel)  in dispc_mgr_go()  argument
574 	WARN_ON(dispc_mgr_is_enabled(channel) == false);  in dispc_mgr_go()
575 	WARN_ON(dispc_mgr_go_busy(channel));  in dispc_mgr_go()
577 	DSSDBG("GO %s\n", mgr_desc[channel].name);  in dispc_mgr_go()
579 	mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);  in dispc_mgr_go()
929 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)  in dispc_ovl_set_channel_out()  argument
951 		switch (channel) {  in dispc_ovl_set_channel_out()
981 		val = FLD_MOD(val, channel, shift, shift);  in dispc_ovl_set_channel_out()
991 	enum omap_channel channel;  in dispc_ovl_get_channel_out()  local
1011 			channel = FLD_GET(val, shift, shift);  in dispc_ovl_get_channel_out()
1013 			channel = OMAP_DSS_CHANNEL_LCD2;  in dispc_ovl_get_channel_out()
1015 			channel = OMAP_DSS_CHANNEL_LCD3;  in dispc_ovl_get_channel_out()
1018 			channel = FLD_GET(val, shift, shift);  in dispc_ovl_get_channel_out()
1020 			channel = OMAP_DSS_CHANNEL_LCD2;  in dispc_ovl_get_channel_out()
1022 		channel = FLD_GET(val, shift, shift);  in dispc_ovl_get_channel_out()
1025 	return channel;  in dispc_ovl_get_channel_out()
1028 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)  in dispc_wb_set_channel_in()  argument
1032 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);  in dispc_wb_set_channel_in()
1076 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)  in dispc_mgr_enable_cpr()  argument
1078 	if (channel == OMAP_DSS_CHANNEL_DIGIT)  in dispc_mgr_enable_cpr()
1081 	mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);  in dispc_mgr_enable_cpr()
1084 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,  in dispc_mgr_set_cpr_coef()  argument
1089 	if (!dss_mgr_is_lcd(channel))  in dispc_mgr_set_cpr_coef()
1099 	dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);  in dispc_mgr_set_cpr_coef()
1100 	dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);  in dispc_mgr_set_cpr_coef()
1101 	dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);  in dispc_mgr_set_cpr_coef()
1128 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,  in dispc_mgr_set_size()  argument
1136 	dispc_write_reg(DISPC_SIZE_MGR(channel), val);  in dispc_mgr_set_size()
2511 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,  in dispc_ovl_check()  argument
2524 	unsigned long pclk = dispc_mgr_pclk_rate(channel);  in dispc_ovl_check()
2525 	unsigned long lclk = dispc_mgr_lclk_rate(channel);  in dispc_ovl_check()
2753 	enum omap_channel channel;  in dispc_ovl_setup()  local
2755 	channel = dispc_ovl_get_channel_out(plane);  in dispc_ovl_setup()
2761 		oi->color_mode, oi->rotation, oi->mirror, channel, replication);  in dispc_ovl_setup()
2840 void dispc_mgr_enable(enum omap_channel channel, bool enable)  in dispc_mgr_enable()  argument
2842 	mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);  in dispc_mgr_enable()
2844 	mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);  in dispc_mgr_enable()
2848 bool dispc_mgr_is_enabled(enum omap_channel channel)  in dispc_mgr_is_enabled()  argument
2850 	return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);  in dispc_mgr_is_enabled()
2888 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)  in dispc_mgr_enable_fifohandcheck()  argument
2890 	mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);  in dispc_mgr_enable_fifohandcheck()
2894 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)  in dispc_mgr_set_lcd_type_tft()  argument
2896 	mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);  in dispc_mgr_set_lcd_type_tft()
2905 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)  in dispc_mgr_set_default_color()  argument
2907 	dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);  in dispc_mgr_set_default_color()
2936 void dispc_mgr_setup(enum omap_channel channel,  in dispc_mgr_setup()  argument
2939 	dispc_mgr_set_default_color(channel, info->default_color);  in dispc_mgr_setup()
2940 	dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);  in dispc_mgr_setup()
2941 	dispc_mgr_enable_trans_key(channel, info->trans_enabled);  in dispc_mgr_setup()
2942 	dispc_mgr_enable_alpha_fixed_zorder(channel,  in dispc_mgr_setup()
2945 		dispc_mgr_enable_cpr(channel, info->cpr_enable);  in dispc_mgr_setup()
2946 		dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);  in dispc_mgr_setup()
2951 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)  in dispc_mgr_set_tft_data_lines()  argument
2973 	mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);  in dispc_mgr_set_tft_data_lines()
3005 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)  in dispc_mgr_enable_stallmode()  argument
3007 	mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);  in dispc_mgr_enable_stallmode()
3010 void dispc_mgr_set_lcd_config(enum omap_channel channel,  in dispc_mgr_set_lcd_config()  argument
3015 	dispc_mgr_enable_stallmode(channel, config->stallmode);  in dispc_mgr_set_lcd_config()
3016 	dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);  in dispc_mgr_set_lcd_config()
3018 	dispc_mgr_set_clock_div(channel, &config->clock_info);  in dispc_mgr_set_lcd_config()
3020 	dispc_mgr_set_tft_data_lines(channel, config->video_port_width);  in dispc_mgr_set_lcd_config()
3024 	dispc_mgr_set_lcd_type_tft(channel);  in dispc_mgr_set_lcd_config()
3047 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,  in _dispc_mgr_pclk_ok()  argument
3050 	if (dss_mgr_is_lcd(channel))  in _dispc_mgr_pclk_ok()
3056 bool dispc_mgr_timings_ok(enum omap_channel channel,  in dispc_mgr_timings_ok()  argument
3062 	if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))  in dispc_mgr_timings_ok()
3065 	if (dss_mgr_is_lcd(channel)) {  in dispc_mgr_timings_ok()
3079 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,  in _dispc_mgr_set_lcd_timings()  argument
3098 	dispc_write_reg(DISPC_TIMING_H(channel), timing_h);  in _dispc_mgr_set_lcd_timings()
3099 	dispc_write_reg(DISPC_TIMING_V(channel), timing_v);  in _dispc_mgr_set_lcd_timings()
3166 	dispc_write_reg(DISPC_POL_FREQ(channel), l);  in _dispc_mgr_set_lcd_timings()
3180 		mask <<= 16 + shifts[channel];  in _dispc_mgr_set_lcd_timings()
3181 		val <<= 16 + shifts[channel];  in _dispc_mgr_set_lcd_timings()
3189 void dispc_mgr_set_timings(enum omap_channel channel,  in dispc_mgr_set_timings()  argument
3196 	DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);  in dispc_mgr_set_timings()
3198 	if (!dispc_mgr_timings_ok(channel, &t)) {  in dispc_mgr_set_timings()
3203 	if (dss_mgr_is_lcd(channel)) {  in dispc_mgr_set_timings()
3204 		_dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,  in dispc_mgr_set_timings()
3227 	dispc_mgr_set_size(channel, t.x_res, t.y_res);  in dispc_mgr_set_timings()
3231 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,  in dispc_mgr_set_lcd_divisor()  argument
3237 	dispc_write_reg(DISPC_DIVISORo(channel),  in dispc_mgr_set_lcd_divisor()
3241 			channel == OMAP_DSS_CHANNEL_LCD)  in dispc_mgr_set_lcd_divisor()
3245 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,  in dispc_mgr_get_lcd_divisor()  argument
3249 	l = dispc_read_reg(DISPC_DIVISORo(channel));  in dispc_mgr_get_lcd_divisor()
3285 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)  in dispc_mgr_lclk_rate()  argument
3292 	if (dss_mgr_is_lcd(channel)) {  in dispc_mgr_lclk_rate()
3293 		l = dispc_read_reg(DISPC_DIVISORo(channel));  in dispc_mgr_lclk_rate()
3297 		switch (dss_get_lcd_clk_source(channel)) {  in dispc_mgr_lclk_rate()
3326 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)  in dispc_mgr_pclk_rate()  argument
3330 	if (dss_mgr_is_lcd(channel)) {  in dispc_mgr_pclk_rate()
3334 		l = dispc_read_reg(DISPC_DIVISORo(channel));  in dispc_mgr_pclk_rate()
3338 		r = dispc_mgr_lclk_rate(channel);  in dispc_mgr_pclk_rate()
3358 	enum omap_channel channel;  in dispc_plane_pclk_rate()  local
3363 	channel = dispc_ovl_get_channel_out(plane);  in dispc_plane_pclk_rate()
3365 	return dispc_mgr_pclk_rate(channel);  in dispc_plane_pclk_rate()
3370 	enum omap_channel channel;  in dispc_plane_lclk_rate()  local
3375 	channel	= dispc_ovl_get_channel_out(plane);  in dispc_plane_lclk_rate()
3377 	return dispc_mgr_lclk_rate(channel);  in dispc_plane_lclk_rate()
3380 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)  in dispc_dump_clocks_channel()  argument
3385 	seq_printf(s, "- %s -\n", mgr_desc[channel].name);  in dispc_dump_clocks_channel()
3387 	lcd_clk_src = dss_get_lcd_clk_source(channel);  in dispc_dump_clocks_channel()
3389 	seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,  in dispc_dump_clocks_channel()
3393 	dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);  in dispc_dump_clocks_channel()
3396 		dispc_mgr_lclk_rate(channel), lcd);  in dispc_dump_clocks_channel()
3398 		dispc_mgr_pclk_rate(channel), pcd);  in dispc_dump_clocks_channel()
3677 void dispc_mgr_set_clock_div(enum omap_channel channel,  in dispc_mgr_set_clock_div()  argument
3683 	dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);  in dispc_mgr_set_clock_div()
3686 int dispc_mgr_get_clock_div(enum omap_channel channel,  in dispc_mgr_get_clock_div()  argument
3693 	cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);  in dispc_mgr_get_clock_div()
3694 	cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);  in dispc_mgr_get_clock_div()