62 #define REG_FLD_MOD(idx, val, start, end)				\  macro
277 	REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);  in mgr_fld_write()
604 	REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);  in dispc_wb_go()
701 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);  in dispc_ovl_write_color_conv_coef()
790 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);  in dispc_ovl_set_zorder()
801 		REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);  in dispc_ovl_enable_zorder_planes()
810 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);  in dispc_ovl_set_pre_mult_alpha()
823 	REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);  in dispc_ovl_setup_global_alpha()
914 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);  in dispc_ovl_set_color_mode()
924 		REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);  in dispc_ovl_configure_burst_type()
926 		REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);  in dispc_ovl_configure_burst_type()
1032 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);  in dispc_wb_set_channel_in()
1042 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);  in dispc_ovl_set_burst_size()
1073 	REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);  in dispc_enable_gamma_table()
1125 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);  in dispc_ovl_enable_replication()
1261 	REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);  in dispc_enable_fifomerge()
1321 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);  in dispc_ovl_set_mflag()
1614 			REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);  in dispc_ovl_set_scaling_uv()
1667 		REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),  in dispc_ovl_set_scaling_uv()
1671 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);  in dispc_ovl_set_scaling_uv()
1673 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);  in dispc_ovl_set_scaling_uv()
1757 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);  in dispc_ovl_set_rotation_attrs()
1759 		REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),  in dispc_ovl_set_rotation_attrs()
1767 		REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);  in dispc_ovl_set_rotation_attrs()
2828 	REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);  in dispc_ovl_enable()
2869 	REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);  in dispc_lcd_enable_signal_polarity()
2877 	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);  in dispc_lcd_enable_signal()
2885 	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);  in dispc_pck_free_enable()
2901 	REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);  in dispc_set_loadmode()
2931 		REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);  in dispc_mgr_enable_alpha_fixed_zorder()
2933 		REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);  in dispc_mgr_enable_alpha_fixed_zorder()
3733 	REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);	/* SIDLEMODE: smart idle */  in dispc_enable_sidle()
3738 	REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);	/* SIDLEMODE: no idle */  in dispc_disable_sidle()
3758 		REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);  in _omap_dispc_initial_config()
3771 		REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);  in _omap_dispc_initial_config()