174 	int r;  in td028ttec1_panel_connect()  local
179 	r = in->ops.dpi->connect(in, dssdev);  in td028ttec1_panel_connect()
180 	if (r)  in td028ttec1_panel_connect()
181 		return r;  in td028ttec1_panel_connect()
201 	int r;  in td028ttec1_panel_enable()  local
213 	r = in->ops.dpi->enable(in);  in td028ttec1_panel_enable()
214 	if (r)  in td028ttec1_panel_enable()
215 		return r;  in td028ttec1_panel_enable()
221 	r |= jbt_ret_write_0(ddata, 0x00);  in td028ttec1_panel_enable()
223 	r |= jbt_ret_write_0(ddata, 0x00);  in td028ttec1_panel_enable()
225 	r |= jbt_ret_write_0(ddata, 0x00);  in td028ttec1_panel_enable()
228 	if (r) {  in td028ttec1_panel_enable()
234 	r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);  in td028ttec1_panel_enable()
237 	r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);  in td028ttec1_panel_enable()
240 	r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);  in td028ttec1_panel_enable()
243 	r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);  in td028ttec1_panel_enable()
246 	r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);  in td028ttec1_panel_enable()
249 	r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);  in td028ttec1_panel_enable()
254 	r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);  in td028ttec1_panel_enable()
255 	r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);  in td028ttec1_panel_enable()
256 	r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);  in td028ttec1_panel_enable()
257 	r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);  in td028ttec1_panel_enable()
258 	r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);  in td028ttec1_panel_enable()
259 	r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);  in td028ttec1_panel_enable()
260 	r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);  in td028ttec1_panel_enable()
261 	r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);  in td028ttec1_panel_enable()
262 	r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);  in td028ttec1_panel_enable()
263 	r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);  in td028ttec1_panel_enable()
264 	r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);  in td028ttec1_panel_enable()
265 	r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);  in td028ttec1_panel_enable()
266 	r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);  in td028ttec1_panel_enable()
271 	r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);  in td028ttec1_panel_enable()
272 	r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);  in td028ttec1_panel_enable()
274 	r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);  in td028ttec1_panel_enable()
275 	r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);  in td028ttec1_panel_enable()
276 	r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);  in td028ttec1_panel_enable()
277 	r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);  in td028ttec1_panel_enable()
278 	r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);  in td028ttec1_panel_enable()
279 	r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);  in td028ttec1_panel_enable()
280 	r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);  in td028ttec1_panel_enable()
282 	r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);  in td028ttec1_panel_enable()
283 	r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);  in td028ttec1_panel_enable()
284 	r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);  in td028ttec1_panel_enable()
285 	r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);  in td028ttec1_panel_enable()
287 	r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);  in td028ttec1_panel_enable()
288 	r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);  in td028ttec1_panel_enable()
289 	r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);  in td028ttec1_panel_enable()
291 	r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);  in td028ttec1_panel_enable()
292 	r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);  in td028ttec1_panel_enable()
294 	r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);  in td028ttec1_panel_enable()
295 	r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);  in td028ttec1_panel_enable()
296 	r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);  in td028ttec1_panel_enable()
298 	r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);  in td028ttec1_panel_enable()
304 	return r ? -EIO : 0;  in td028ttec1_panel_enable()
414 	int r;  in td028ttec1_panel_probe()  local
421 	r = spi_setup(spi);  in td028ttec1_panel_probe()
422 	if (r < 0) {  in td028ttec1_panel_probe()
423 		dev_err(&spi->dev, "spi_setup failed: %d\n", r);  in td028ttec1_panel_probe()
424 		return r;  in td028ttec1_panel_probe()
436 		r = td028ttec1_panel_probe_pdata(spi);  in td028ttec1_panel_probe()
437 		if (r)  in td028ttec1_panel_probe()
438 			return r;  in td028ttec1_panel_probe()
440 		r = td028ttec1_probe_of(spi);  in td028ttec1_panel_probe()
441 		if (r)  in td028ttec1_panel_probe()
442 			return r;  in td028ttec1_panel_probe()
457 	r = omapdss_register_display(dssdev);  in td028ttec1_panel_probe()
458 	if (r) {  in td028ttec1_panel_probe()
467 	return r;  in td028ttec1_panel_probe()