Lines Matching refs:par
114 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8, in nvidiafb_load_cursor_image() argument
140 NV_WR32(&par->CURSOR[k++], 0, tmp); in nvidiafb_load_cursor_image()
146 static void nvidia_write_clut(struct nvidia_par *par, in nvidia_write_clut() argument
149 NVWriteDacMask(par, 0xff); in nvidia_write_clut()
150 NVWriteDacWriteAddr(par, regnum); in nvidia_write_clut()
151 NVWriteDacData(par, red); in nvidia_write_clut()
152 NVWriteDacData(par, green); in nvidia_write_clut()
153 NVWriteDacData(par, blue); in nvidia_write_clut()
156 static void nvidia_read_clut(struct nvidia_par *par, in nvidia_read_clut() argument
159 NVWriteDacMask(par, 0xff); in nvidia_read_clut()
160 NVWriteDacReadAddr(par, regnum); in nvidia_read_clut()
161 *red = NVReadDacData(par); in nvidia_read_clut()
162 *green = NVReadDacData(par); in nvidia_read_clut()
163 *blue = NVReadDacData(par); in nvidia_read_clut()
166 static int nvidia_panel_tweak(struct nvidia_par *par, in nvidia_panel_tweak() argument
171 if (par->paneltweak) { in nvidia_panel_tweak()
172 tweak = par->paneltweak; in nvidia_panel_tweak()
180 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) { in nvidia_panel_tweak()
185 if((par->Chipset & 0xfff0) == 0x0310) { in nvidia_panel_tweak()
194 static void nvidia_screen_off(struct nvidia_par *par, int on) in nvidia_screen_off() argument
202 tmp = NVReadSeq(par, 0x01); in nvidia_screen_off()
204 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */ in nvidia_screen_off()
205 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */ in nvidia_screen_off()
211 tmp = NVReadSeq(par, 0x01); in nvidia_screen_off()
213 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */ in nvidia_screen_off()
214 NVWriteSeq(par, 0x00, 0x03); /* End Reset */ in nvidia_screen_off()
218 static void nvidia_save_vga(struct nvidia_par *par, in nvidia_save_vga() argument
224 NVLockUnlock(par, 0); in nvidia_save_vga()
226 NVUnloadStateExt(par, state); in nvidia_save_vga()
228 state->misc_output = NVReadMiscOut(par); in nvidia_save_vga()
231 state->crtc[i] = NVReadCrtc(par, i); in nvidia_save_vga()
234 state->attr[i] = NVReadAttr(par, i); in nvidia_save_vga()
237 state->gra[i] = NVReadGr(par, i); in nvidia_save_vga()
240 state->seq[i] = NVReadSeq(par, i); in nvidia_save_vga()
246 static void nvidia_write_regs(struct nvidia_par *par, in nvidia_write_regs() argument
253 NVLoadStateExt(par, state); in nvidia_write_regs()
255 NVWriteMiscOut(par, state->misc_output); in nvidia_write_regs()
261 NVWriteSeq(par, i, state->seq[i]); in nvidia_write_regs()
265 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80); in nvidia_write_regs()
276 NVWriteCrtc(par, i, state->crtc[i]); in nvidia_write_regs()
284 NVWriteGr(par, i, state->gra[i]); in nvidia_write_regs()
291 NVWriteAttr(par, i, state->attr[i]); in nvidia_write_regs()
299 struct nvidia_par *par = info->par; in nvidia_calc_regs() local
300 struct _riva_hw_state *state = &par->ModeReg; in nvidia_calc_regs()
326 if (par->FlatPanel == 1) { in nvidia_calc_regs()
365 if (par->Television) in nvidia_calc_regs()
401 if (par->Architecture >= NV_ARCH_10) in nvidia_calc_regs()
402 par->CURSOR = (volatile u32 __iomem *)(info->screen_base + in nvidia_calc_regs()
403 par->CursorStart); in nvidia_calc_regs()
414 NVCalcStateExt(par, state, i, info->var.xres_virtual, in nvidia_calc_regs()
418 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff; in nvidia_calc_regs()
419 if (par->FlatPanel == 1) { in nvidia_calc_regs()
422 if (!par->fpScaler || (par->fpWidth <= info->var.xres) in nvidia_calc_regs()
423 || (par->fpHeight <= info->var.yres)) { in nvidia_calc_regs()
427 if (!par->crtcSync_read) { in nvidia_calc_regs()
428 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828); in nvidia_calc_regs()
429 par->crtcSync_read = 1; in nvidia_calc_regs()
432 par->PanelTweak = nvidia_panel_tweak(par, state); in nvidia_calc_regs()
440 VGA_WR08(par->PCIO, 0x03D4, 0x1C); in nvidia_calc_regs()
441 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5); in nvidia_calc_regs()
443 if (par->CRTCnumber) { in nvidia_calc_regs()
444 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000; in nvidia_calc_regs()
445 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000; in nvidia_calc_regs()
448 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508); in nvidia_calc_regs()
449 if (par->twoStagePLL) in nvidia_calc_regs()
450 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578); in nvidia_calc_regs()
451 } else if (par->twoHeads) { in nvidia_calc_regs()
452 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000; in nvidia_calc_regs()
453 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000; in nvidia_calc_regs()
455 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); in nvidia_calc_regs()
456 if (par->twoStagePLL) in nvidia_calc_regs()
457 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); in nvidia_calc_regs()
465 if (par->alphaCursor) { in nvidia_calc_regs()
466 if ((par->Chipset & 0x0ff0) != 0x0110) in nvidia_calc_regs()
474 if (par->twoHeads) { in nvidia_calc_regs()
475 if ((par->Chipset & 0x0ff0) == 0x0110) { in nvidia_calc_regs()
476 state->dither = NV_RD32(par->PRAMDAC, 0x0528) & in nvidia_calc_regs()
478 if (par->FPDither) in nvidia_calc_regs()
481 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1; in nvidia_calc_regs()
482 if (par->FPDither) in nvidia_calc_regs()
496 struct nvidia_par *par = info->par; in nvidia_init_vga() local
497 struct _riva_hw_state *state = &par->ModeReg; in nvidia_init_vga()
531 struct nvidia_par *par = info->par; in nvidiafb_cursor() local
539 NVShowHideCursor(par, 0); in nvidiafb_cursor()
541 if (par->cursor_reset) { in nvidiafb_cursor()
543 par->cursor_reset = 0; in nvidiafb_cursor()
547 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2); in nvidiafb_cursor()
557 NV_WR32(par->PRAMDAC, 0x0000300, temp); in nvidiafb_cursor()
595 NVLockUnlock(par, 0); in nvidiafb_cursor()
597 nvidiafb_load_cursor_image(par, data, bg, fg, in nvidiafb_cursor()
605 NVShowHideCursor(par, 1); in nvidiafb_cursor()
612 struct nvidia_par *par = info->par; in nvidiafb_set_par() local
616 NVLockUnlock(par, 1); in nvidiafb_set_par()
617 if (!par->FlatPanel || !par->twoHeads) in nvidiafb_set_par()
618 par->FPDither = 0; in nvidiafb_set_par()
620 if (par->FPDither < 0) { in nvidiafb_set_par()
621 if ((par->Chipset & 0x0ff0) == 0x0110) in nvidiafb_set_par()
622 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528) in nvidiafb_set_par()
625 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1); in nvidiafb_set_par()
627 par->FPDither ? "enabled" : "disabled"); in nvidiafb_set_par()
636 NVLockUnlock(par, 0); in nvidiafb_set_par()
637 if (par->twoHeads) { in nvidiafb_set_par()
638 VGA_WR08(par->PCIO, 0x03D4, 0x44); in nvidiafb_set_par()
639 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner); in nvidiafb_set_par()
640 NVLockUnlock(par, 0); in nvidiafb_set_par()
643 nvidia_screen_off(par, 1); in nvidiafb_set_par()
645 nvidia_write_regs(par, &par->ModeReg); in nvidiafb_set_par()
646 NVSetStartAddress(par, 0); in nvidiafb_set_par()
653 VGA_WR08(par->PCIO, 0x3d4, 0x46); in nvidiafb_set_par()
654 tmp = VGA_RD08(par->PCIO, 0x3d5); in nvidiafb_set_par()
656 VGA_WR08(par->PCIO, 0x3d5, tmp); in nvidiafb_set_par()
681 par->cursor_reset = 1; in nvidiafb_set_par()
683 nvidia_screen_off(par, 0); in nvidiafb_set_par()
692 NVLockUnlock(par, 0); in nvidiafb_set_par()
701 struct nvidia_par *par = info->par; in nvidiafb_setcolreg() local
723 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); in nvidiafb_setcolreg()
728 nvidia_write_clut(par, regno * 8 + i, red >> 8, in nvidiafb_setcolreg()
736 nvidia_write_clut(par, regno * 8 + i, in nvidiafb_setcolreg()
742 nvidia_read_clut(par, regno * 4, &r, &g, &b); in nvidiafb_setcolreg()
745 nvidia_write_clut(par, regno * 4 + i, r, in nvidiafb_setcolreg()
750 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); in nvidiafb_setcolreg()
764 struct nvidia_par *par = info->par; in nvidiafb_check_var() local
848 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres || in nvidiafb_check_var()
849 par->fpHeight < var->yres)) { in nvidiafb_check_var()
852 var->xres = par->fpWidth; in nvidiafb_check_var()
853 var->yres = par->fpHeight; in nvidiafb_check_var()
917 struct nvidia_par *par = info->par; in nvidiafb_pan_display() local
922 NVSetStartAddress(par, total); in nvidiafb_pan_display()
929 struct nvidia_par *par = info->par; in nvidiafb_blank() local
932 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */ in nvidiafb_blank()
933 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */ in nvidiafb_blank()
955 NVWriteSeq(par, 0x01, tmp); in nvidiafb_blank()
956 NVWriteCrtc(par, 0x1a, vesa); in nvidiafb_blank()
970 static void save_vga_x86(struct nvidia_par *par) in save_vga_x86() argument
972 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; in save_vga_x86()
975 memset(&par->vgastate, 0, sizeof(par->vgastate)); in save_vga_x86()
976 par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | in save_vga_x86()
978 save_vga(&par->vgastate); in save_vga_x86()
982 static void restore_vga_x86(struct nvidia_par *par) in restore_vga_x86() argument
984 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; in restore_vga_x86()
987 restore_vga(&par->vgastate); in restore_vga_x86()
996 struct nvidia_par *par = info->par; in nvidiafb_open() local
998 if (!par->open_count) { in nvidiafb_open()
999 save_vga_x86(par); in nvidiafb_open()
1000 nvidia_save_vga(par, &par->initial_state); in nvidiafb_open()
1003 par->open_count++; in nvidiafb_open()
1009 struct nvidia_par *par = info->par; in nvidiafb_release() local
1012 if (!par->open_count) { in nvidiafb_release()
1017 if (par->open_count == 1) { in nvidiafb_release()
1018 nvidia_write_regs(par, &par->initial_state); in nvidiafb_release()
1019 restore_vga_x86(par); in nvidiafb_release()
1022 par->open_count--; in nvidiafb_release()
1047 struct nvidia_par *par = info->par; in nvidiafb_suspend() local
1052 par->pm_state = mesg.event; in nvidiafb_suspend()
1057 nvidia_write_regs(par, &par->SavedReg); in nvidiafb_suspend()
1071 struct nvidia_par *par = info->par; in nvidiafb_resume() local
1076 if (par->pm_state != PM_EVENT_FREEZE) { in nvidiafb_resume()
1085 par->pm_state = PM_EVENT_ON; in nvidiafb_resume()
1103 struct nvidia_par *par = info->par; in nvidia_set_fbinfo() local
1135 } else if (par->fpWidth && par->fpHeight) { in nvidia_set_fbinfo()
1139 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight); in nvidia_set_fbinfo()
1151 info->pseudo_palette = par->pseudo_palette; in nvidia_set_fbinfo()
1172 switch (par->Architecture) { in nvidia_set_fbinfo()
1197 struct nvidia_par *par = info->par; in nvidia_get_chipset() local
1198 u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device; in nvidia_get_chipset()
1205 id = NV_RD32(par->REGS, 0x1800); in nvidia_get_chipset()
1220 struct nvidia_par *par = info->par; in nvidia_get_arch() local
1223 switch (par->Chipset & 0x0ff0) { in nvidia_get_arch()
1272 struct nvidia_par *par; in nvidiafb_probe() local
1285 par = info->par; in nvidiafb_probe()
1286 par->pci_dev = pd; in nvidiafb_probe()
1302 par->FlatPanel = flatpanel; in nvidiafb_probe()
1305 par->FPDither = fpdither; in nvidiafb_probe()
1307 par->CRTCnumber = forceCRTC; in nvidiafb_probe()
1308 par->FpScale = (!noscale); in nvidiafb_probe()
1309 par->paneltweak = paneltweak; in nvidiafb_probe()
1310 par->reverse_i2c = reverse_i2c; in nvidiafb_probe()
1321 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); in nvidiafb_probe()
1323 if (!par->REGS) { in nvidiafb_probe()
1328 par->Chipset = nvidia_get_chipset(info); in nvidiafb_probe()
1329 par->Architecture = nvidia_get_arch(info); in nvidiafb_probe()
1331 if (par->Architecture == 0) { in nvidiafb_probe()
1341 par->FbAddress = nvidiafb_fix.smem_start; in nvidiafb_probe()
1342 par->FbMapSize = par->RamAmountKBytes * 1024; in nvidiafb_probe()
1343 if (vram && vram * 1024 * 1024 < par->FbMapSize) in nvidiafb_probe()
1344 par->FbMapSize = vram * 1024 * 1024; in nvidiafb_probe()
1347 if (par->FbMapSize > 64 * 1024 * 1024) in nvidiafb_probe()
1348 par->FbMapSize = 64 * 1024 * 1024; in nvidiafb_probe()
1350 if(par->Architecture >= NV_ARCH_40) in nvidiafb_probe()
1351 par->FbUsableSize = par->FbMapSize - (560 * 1024); in nvidiafb_probe()
1353 par->FbUsableSize = par->FbMapSize - (128 * 1024); in nvidiafb_probe()
1354 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 : in nvidiafb_probe()
1356 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize; in nvidiafb_probe()
1357 par->CursorStart = par->FbUsableSize + (32 * 1024); in nvidiafb_probe()
1360 par->FbMapSize); in nvidiafb_probe()
1361 info->screen_size = par->FbUsableSize; in nvidiafb_probe()
1362 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024; in nvidiafb_probe()
1369 par->FbStart = info->screen_base; in nvidiafb_probe()
1372 par->wc_cookie = arch_phys_wc_add(nvidiafb_fix.smem_start, in nvidiafb_probe()
1373 par->RamAmountKBytes * 1024); in nvidiafb_probe()
1383 nvidia_save_vga(par, &par->SavedReg); in nvidiafb_probe()
1388 nvidia_bl_init(par); in nvidiafb_probe()
1399 par->FbMapSize / (1024 * 1024), info->fix.smem_start); in nvidiafb_probe()
1408 nvidia_delete_i2c_busses(par); in nvidiafb_probe()
1410 iounmap(par->REGS); in nvidiafb_probe()
1424 struct nvidia_par *par = info->par; in nvidiafb_remove() local
1430 nvidia_bl_exit(par); in nvidiafb_remove()
1431 arch_phys_wc_del(par->wc_cookie); in nvidiafb_remove()
1434 nvidia_delete_i2c_busses(par); in nvidiafb_remove()
1435 iounmap(par->REGS); in nvidiafb_remove()