55 			writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR);  in ctrl_handle_irq()
139 	writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_set_fmt()
152 		writel_relaxed(win->pitch[0], &regs->v_pitch_yc);  in overlay_set_win()
153 		writel_relaxed(win->pitch[2] << 16 |  in overlay_set_win()
156 		writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->v_size);  in overlay_set_win()
157 		writel_relaxed((win->ydst << 16) | win->xdst, &regs->v_size_z);  in overlay_set_win()
158 		writel_relaxed(win->ypos << 16 | win->xpos, &regs->v_start);  in overlay_set_win()
160 		writel_relaxed(win->pitch[0], &regs->g_pitch);  in overlay_set_win()
162 		writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->g_size);  in overlay_set_win()
163 		writel_relaxed((win->ydst << 16) | win->xdst, &regs->g_size_z);  in overlay_set_win()
164 		writel_relaxed(win->ypos << 16 | win->xpos, &regs->g_start);  in overlay_set_win()
196 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_enabledisable()
249 		writel_relaxed(addr->phys[0], &regs->v_y0);  in overlay_set_addr()
250 		writel_relaxed(addr->phys[1], &regs->v_u0);  in overlay_set_addr()
251 		writel_relaxed(addr->phys[2], &regs->v_v0);  in overlay_set_addr()
253 		writel_relaxed(addr->phys[0], &regs->g_0);  in overlay_set_addr()
276 	writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));  in path_set_mode()
282 	writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));  in path_set_mode()
284 	writel_relaxed((mode->yres << 16) | mode->xres, &regs->screen_active);  in path_set_mode()
285 	writel_relaxed((mode->left_margin << 16) | mode->right_margin,  in path_set_mode()
287 	writel_relaxed((mode->upper_margin << 16) | mode->lower_margin,  in path_set_mode()
293 	writel_relaxed((total_y << 16) | total_x, &regs->screen_size);  in path_set_mode()
301 	writel_relaxed(vsync_ctrl, &regs->vsync_ctrl);  in path_set_mode()
315 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_set_mode()
337 	writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL);  in ctrl_set_default()
346 	writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA);  in ctrl_set_default()
362 		writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);  in path_set_default()
369 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_set_default()
379 	writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));  in path_set_default()
382 	writel_relaxed(0x00000000, &regs->blank_color);  in path_set_default()
383 	writel_relaxed(0x00000000, &regs->g_1);  in path_set_default()
384 	writel_relaxed(0x00000000, &regs->g_start);  in path_set_default()
396 	writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in path_set_default()