46 	u32 isr, imask, tmp;  in ctrl_handle_irq()  local
53 		tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);  in ctrl_handle_irq()
54 		if (tmp & isr)  in ctrl_handle_irq()
134 	u32 tmp;  in dmafetch_set_fmt()  local
136 	tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_set_fmt()
137 	tmp &= ~dma_mask(overlay_is_vid(overlay));  in dmafetch_set_fmt()
138 	tmp |= fmt_to_reg(overlay, overlay->win.pix_fmt);  in dmafetch_set_fmt()
139 	writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_set_fmt()
176 	u32 tmp;  in dmafetch_onoff()  local
180 	tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_onoff()
181 	tmp &= ~mask;  in dmafetch_onoff()
182 	tmp |= (on ? enable : 0);  in dmafetch_onoff()
183 	writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_onoff()
189 	u32 tmp;  in path_enabledisable()  local
191 	tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));  in path_enabledisable()
193 		tmp &= ~SCLK_DISABLE;  in path_enabledisable()
195 		tmp |= SCLK_DISABLE;  in path_enabledisable()
196 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_enabledisable()
261 	u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div,  in path_set_mode()  local
271 	tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1;  in path_set_mode()
272 	tmp |= mode->vsync_invert ? 0 : 0x8;  in path_set_mode()
273 	tmp |= mode->hsync_invert ? 0 : 0x4;  in path_set_mode()
274 	tmp |= link_config & CFG_DUMBMODE_MASK;  in path_set_mode()
275 	tmp |= CFG_DUMB_ENA(1);  in path_set_mode()
276 	writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));  in path_set_mode()
279 	tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) &  in path_set_mode()
281 	tmp |= dsi_rbswap & CFG_INTFRBSWAP_MASK;  in path_set_mode()
282 	writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));  in path_set_mode()
312 	tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));  in path_set_mode()
313 	tmp &= ~CLK_INT_DIV_MASK;  in path_set_mode()
314 	tmp |= sclk_div;  in path_set_mode()
315 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_set_mode()
329 	u32 tmp, irq_mask;  in ctrl_set_default()  local
335 	tmp = readl_relaxed(ctrl->reg_base + LCD_TOP_CTRL);  in ctrl_set_default()
336 	tmp |= 0xfff0;  in ctrl_set_default()
337 	writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL);  in ctrl_set_default()
343 	tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);  in ctrl_set_default()
344 	tmp &= ~irq_mask;  in ctrl_set_default()
345 	tmp |= irq_mask;  in ctrl_set_default()
346 	writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA);  in ctrl_set_default()
352 	u32 dma_ctrl1, mask, tmp, path_config;  in path_set_default()  local
359 		tmp = readl_relaxed(ctrl_regs(path) + SPU_IOPAD_CONTROL);  in path_set_default()
360 		tmp &= ~mask;  in path_set_default()
361 		tmp |= path_config;  in path_set_default()
362 		writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);  in path_set_default()
366 	tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));  in path_set_default()
367 	tmp &= ~SCLK_SRC_SEL_MASK;  in path_set_default()
368 	tmp |= path_config;  in path_set_default()
369 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_set_default()
392 	tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));  in path_set_default()
393 	tmp |= mask;  in path_set_default()
395 		tmp &= ~CFG_ARBFAST_ENA(1);  in path_set_default()
396 	writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in path_set_default()