136 	tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_set_fmt()
139 	writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_set_fmt()
180 	tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_onoff()
183 	writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_onoff()
191 	tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));  in path_enabledisable()
196 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_enabledisable()
271 	tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1;  in path_set_mode()
276 	writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));  in path_set_mode()
279 	tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) &  in path_set_mode()
282 	writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));  in path_set_mode()
312 	tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));  in path_set_mode()
315 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_set_mode()
359 		tmp = readl_relaxed(ctrl_regs(path) + SPU_IOPAD_CONTROL);  in path_set_default()
362 		writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);  in path_set_default()
366 	tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));  in path_set_default()
369 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_set_default()
379 	writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));  in path_set_default()
392 	tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));  in path_set_default()
396 	writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in path_set_default()