69 	u32 tmp;  in intelfbhw_get_chipset()  local
92 		tmp = 0;  in intelfbhw_get_chipset()
95 		pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);  in intelfbhw_get_chipset()
96 		switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &  in intelfbhw_get_chipset()
177 	u16 tmp;  in intelfbhw_get_memory()  local
190 	tmp = 0;  in intelfbhw_get_memory()
191 	pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);  in intelfbhw_get_memory()
211 		if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)  in intelfbhw_get_memory()
224 		switch (tmp & INTEL_830_GMCH_GMS_MASK) {  in intelfbhw_get_memory()
242 				tmp & INTEL_830_GMCH_GMS_MASK);  in intelfbhw_get_memory()
247 		switch (tmp & INTEL_855_GMCH_GMS_MASK) {  in intelfbhw_get_memory()
274 				tmp & INTEL_855_GMCH_GMS_MASK);  in intelfbhw_get_memory()
315 	int tmp;  in intelfbhw_validate_mode()  local
326 	tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;  in intelfbhw_validate_mode()
327 	if (tmp > dinfo->fb.size) {  in intelfbhw_validate_mode()
330 			BtoKB(tmp), BtoKB(dinfo->fb.size));  in intelfbhw_validate_mode()
366 	tmp = 1000000000 / var->pixclock;  in intelfbhw_validate_mode()
367 	if (tmp < MIN_CLOCK) {  in intelfbhw_validate_mode()
369 			(tmp + 500) / 1000, MIN_CLOCK / 1000);  in intelfbhw_validate_mode()
372 	if (tmp > MAX_CLOCK) {  in intelfbhw_validate_mode()
374 			(tmp + 500) / 1000, MAX_CLOCK / 1000);  in intelfbhw_validate_mode()
418 	u32 tmp;  in intelfbhw_do_blank()  local
425 	tmp = INREG(DSPACNTR);  in intelfbhw_do_blank()
427 		tmp &= ~DISPPLANE_PLANE_ENABLE;  in intelfbhw_do_blank()
429 		tmp |= DISPPLANE_PLANE_ENABLE;  in intelfbhw_do_blank()
430 	OUTREG(DSPACNTR, tmp);  in intelfbhw_do_blank()
432 	tmp = INREG(DSPABASE);  in intelfbhw_do_blank()
433 	OUTREG(DSPABASE, tmp);  in intelfbhw_do_blank()
449 	tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;  in intelfbhw_do_blank()
453 		tmp |= ADPA_DPMS_D0;  in intelfbhw_do_blank()
456 		tmp |= ADPA_DPMS_D1;  in intelfbhw_do_blank()
459 		tmp |= ADPA_DPMS_D2;  in intelfbhw_do_blank()
462 		tmp |= ADPA_DPMS_D3;  in intelfbhw_do_blank()
465 	OUTREG(ADPA, tmp);  in intelfbhw_do_blank()
1283 	u32 tmp;  in intelfbhw_program_mode()  local
1299 	tmp = INREG(VGACNTRL);  in intelfbhw_program_mode()
1300 	tmp |= VGA_DISABLE;  in intelfbhw_program_mode()
1301 	OUTREG(VGACNTRL, tmp);  in intelfbhw_program_mode()
1356 	tmp = INREG(pipe_conf_reg);  in intelfbhw_program_mode()
1357 	tmp &= ~PIPECONF_ENABLE;  in intelfbhw_program_mode()
1358 	OUTREG(pipe_conf_reg, tmp);  in intelfbhw_program_mode()
1368 			tmp = INREG(pipe_conf_reg);  in intelfbhw_program_mode()
1369 			tmp &= ~PIPECONF_ENABLE;  in intelfbhw_program_mode()
1370 			OUTREG(pipe_conf_reg, tmp);  in intelfbhw_program_mode()
1377 	tmp = INREG(DSPACNTR);  in intelfbhw_program_mode()
1378 	tmp &= ~DISPPLANE_PLANE_ENABLE;  in intelfbhw_program_mode()
1379 	OUTREG(DSPACNTR, tmp);  in intelfbhw_program_mode()
1380 	tmp = INREG(DSPBCNTR);  in intelfbhw_program_mode()
1381 	tmp &= ~DISPPLANE_PLANE_ENABLE;  in intelfbhw_program_mode()
1382 	OUTREG(DSPBCNTR, tmp);  in intelfbhw_program_mode()
1392 	tmp = INREG(ADPA);  in intelfbhw_program_mode()
1393 	tmp &= ~ADPA_DPMS_CONTROL_MASK;  in intelfbhw_program_mode()
1394 	tmp |= ADPA_DPMS_D3;  in intelfbhw_program_mode()
1395 	OUTREG(ADPA, tmp);  in intelfbhw_program_mode()
1401 	tmp = INREG(dpll_reg);  in intelfbhw_program_mode()
1402 	tmp &= ~DPLL_VCO_ENABLE;  in intelfbhw_program_mode()
1403 	OUTREG(dpll_reg, tmp);  in intelfbhw_program_mode()
1447 	tmp = INREG(ADPA);  in intelfbhw_program_mode()
1448 	tmp &= ~ADPA_DPMS_CONTROL_MASK;  in intelfbhw_program_mode()
1449 	tmp |= ADPA_DPMS_D0;  in intelfbhw_program_mode()
1450 	OUTREG(ADPA, tmp);  in intelfbhw_program_mode()
1459 		tmp = INREG(DSPACNTR);  in intelfbhw_program_mode()
1460 		if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {  in intelfbhw_program_mode()
1461 			tmp |= DISPPLANE_PLANE_ENABLE;  in intelfbhw_program_mode()
1462 			OUTREG(DSPACNTR, tmp);  in intelfbhw_program_mode()
1475 		tmp = INREG(DSPACNTR);  in intelfbhw_program_mode()
1476 		tmp |= DISPPLANE_PLANE_ENABLE;  in intelfbhw_program_mode()
1477 		OUTREG(DSPACNTR, tmp);  in intelfbhw_program_mode()
1590 	u32 tmp;  in reset_state()  local
1600 	tmp = INREG(PRI_RING_LENGTH);  in reset_state()
1601 	if (tmp & RING_ENABLE) {  in reset_state()
1754 	int nbytes, ndwords, pad, tmp;  in intelfbhw_do_drawglyph()  local
1785 	tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;  in intelfbhw_do_drawglyph()
1786 	br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;  in intelfbhw_do_drawglyph()
1841 	u32 tmp;  in intelfbhw_cursor_init()  local
1850 		tmp = INREG(CURSOR_A_CONTROL);  in intelfbhw_cursor_init()
1851 		tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |  in intelfbhw_cursor_init()
1854 		tmp |= CURSOR_MODE_DISABLE;  in intelfbhw_cursor_init()
1855 		OUTREG(CURSOR_A_CONTROL, tmp);  in intelfbhw_cursor_init()
1858 		tmp = INREG(CURSOR_CONTROL);  in intelfbhw_cursor_init()
1859 		tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |  in intelfbhw_cursor_init()
1861 		tmp |= CURSOR_FORMAT_3C;  in intelfbhw_cursor_init()
1862 		OUTREG(CURSOR_CONTROL, tmp);  in intelfbhw_cursor_init()
1864 		tmp = (64 << CURSOR_SIZE_H_SHIFT) |  in intelfbhw_cursor_init()
1866 		OUTREG(CURSOR_SIZE, tmp);  in intelfbhw_cursor_init()
1872 	u32 tmp;  in intelfbhw_cursor_hide()  local
1882 		tmp = INREG(CURSOR_A_CONTROL);  in intelfbhw_cursor_hide()
1883 		tmp &= ~CURSOR_MODE_MASK;  in intelfbhw_cursor_hide()
1884 		tmp |= CURSOR_MODE_DISABLE;  in intelfbhw_cursor_hide()
1885 		OUTREG(CURSOR_A_CONTROL, tmp);  in intelfbhw_cursor_hide()
1889 		tmp = INREG(CURSOR_CONTROL);  in intelfbhw_cursor_hide()
1890 		tmp &= ~CURSOR_ENABLE;  in intelfbhw_cursor_hide()
1891 		OUTREG(CURSOR_CONTROL, tmp);  in intelfbhw_cursor_hide()
1897 	u32 tmp;  in intelfbhw_cursor_show()  local
1911 		tmp = INREG(CURSOR_A_CONTROL);  in intelfbhw_cursor_show()
1912 		tmp &= ~CURSOR_MODE_MASK;  in intelfbhw_cursor_show()
1913 		tmp |= CURSOR_MODE_64_4C_AX;  in intelfbhw_cursor_show()
1914 		OUTREG(CURSOR_A_CONTROL, tmp);  in intelfbhw_cursor_show()
1918 		tmp = INREG(CURSOR_CONTROL);  in intelfbhw_cursor_show()
1919 		tmp |= CURSOR_ENABLE;  in intelfbhw_cursor_show()
1920 		OUTREG(CURSOR_CONTROL, tmp);  in intelfbhw_cursor_show()
1926 	u32 tmp;  in intelfbhw_cursor_setpos()  local
1938 	tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |  in intelfbhw_cursor_setpos()
1940 	OUTREG(CURSOR_A_POSITION, tmp);  in intelfbhw_cursor_setpos()
2010 	u16 tmp;  in intelfbhw_irq()  local
2015 	tmp = INREG16(IIR);  in intelfbhw_irq()
2017 		tmp &= PIPE_A_EVENT_INTERRUPT;  in intelfbhw_irq()
2019 		tmp &= VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */  in intelfbhw_irq()
2021 	if (tmp == 0) {  in intelfbhw_irq()
2029 	OUTREG16(IIR, tmp);  in intelfbhw_irq()
2045 	u16 tmp;  in intelfbhw_enable_irq()  local
2060 		tmp = PIPE_A_EVENT_INTERRUPT;  in intelfbhw_enable_irq()
2062 		tmp = VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */  in intelfbhw_enable_irq()
2063 	if (tmp != INREG16(IER)) {  in intelfbhw_enable_irq()
2064 		DBG_MSG("changing IER to 0x%X\n", tmp);  in intelfbhw_enable_irq()
2065 		OUTREG16(IER, tmp);  in intelfbhw_enable_irq()