Lines Matching refs:FP_DIVISOR_MASK
725 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
726 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
727 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
736 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
737 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
738 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
753 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
754 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
755 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
764 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
765 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
766 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
1129 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter")) in intelfbhw_mode_to_hw()
1131 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter")) in intelfbhw_mode_to_hw()
1133 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter")) in intelfbhw_mode_to_hw()