36 	reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);  in exynos_mipi_dsi_func_reset()
47 	reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);  in exynos_mipi_dsi_sw_reset()
58 	reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);  in exynos_mipi_dsi_sw_reset_release()
67 	return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) &  in exynos_mipi_dsi_get_sw_reset_release()
75 	reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK);  in exynos_mipi_dsi_read_interrupt_mask()
98 	reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);  in exynos_mipi_dsi_init_fifo_pointer()
121 	reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL);  in exynos_mipi_dsi_set_main_stand_by()
137 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) &  in exynos_mipi_dsi_set_main_disp_resol()
153 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) &  in exynos_mipi_dsi_set_main_disp_vporch()
169 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) &  in exynos_mipi_dsi_set_main_disp_hporch()
182 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_MSYNC)) &  in exynos_mipi_dsi_set_main_disp_sync_area()
196 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_SDRESOL)) &  in exynos_mipi_dsi_set_sub_disp_resol()
214 	unsigned int cfg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &  in exynos_mipi_dsi_init_config()
232 	u32 reg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &  in exynos_mipi_dsi_display_config()
258 	reg = readl(dsim->reg_base + EXYNOS_DSIM_CONFIG);  in exynos_mipi_dsi_enable_lane()
283 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR);  in exynos_mipi_dsi_enable_afc()
298 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &  in exynos_mipi_dsi_enable_pll_bypass()
309 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_set_pll_pms()
319 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &  in exynos_mipi_dsi_pll_freq_band()
331 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &  in exynos_mipi_dsi_pll_freq()
348 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &  in exynos_mipi_dsi_enable_pll()
359 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &  in exynos_mipi_dsi_set_byte_clock_src()
370 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &  in exynos_mipi_dsi_enable_byte_clock()
381 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &  in exynos_mipi_dsi_set_esc_clk_prs()
394 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_enable_esc_clk_on_lane()
408 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &  in exynos_mipi_dsi_force_dphy_stop_state()
418 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);  in exynos_mipi_dsi_is_lane_state()
437 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &  in exynos_mipi_dsi_set_stop_state_counter()
448 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &  in exynos_mipi_dsi_set_bta_timeout()
459 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &  in exynos_mipi_dsi_set_lpdr_timeout()
470 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);  in exynos_mipi_dsi_set_cpu_transfer_mode()
483 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);  in exynos_mipi_dsi_set_lcdc_transfer_mode()
496 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &  in exynos_mipi_dsi_enable_hs_clock()
507 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);  in exynos_mipi_dsi_dp_dn_swap()
518 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &  in exynos_mipi_dsi_hs_zero_ctrl()
528 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &  in exynos_mipi_dsi_prep_ctrl()
538 	return readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);  in exynos_mipi_dsi_read_interrupt()
544 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);  in exynos_mipi_dsi_clear_interrupt()
568 	reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);  in exynos_mipi_dsi_is_pll_stable()
575 	return readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL) & ~(0x1f);  in exynos_mipi_dsi_get_fifo_state()
596 	return readl(dsim->reg_base + EXYNOS_DSIM_RXFIFO);  in exynos_mipi_dsi_rd_rx_fifo()
601 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);  in _exynos_mipi_dsi_get_frame_done_status()
608 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);  in _exynos_mipi_dsi_clear_frame_done()