356 	u8 __iomem *regbase;  member
396 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
397 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
402 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
411 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
413 				    caddr_t regbase,
452 	long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;  in cirrusfb_check_mclk()
638 	old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;  in cirrusfb_set_mclk_as_source()
644 		old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;  in cirrusfb_set_mclk_as_source()
648 		vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);  in cirrusfb_set_mclk_as_source()
650 	vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);  in cirrusfb_set_mclk_as_source()
662 	u8 __iomem *regbase = cinfo->regbase;  in cirrusfb_set_par_foo()  local
748 	vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);	/* previously: 0x00) */  in cirrusfb_set_par_foo()
752 	vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);  in cirrusfb_set_par_foo()
755 	vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);  in cirrusfb_set_par_foo()
758 	vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);  in cirrusfb_set_par_foo()
762 	vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,  in cirrusfb_set_par_foo()
766 	vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);  in cirrusfb_set_par_foo()
772 	vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);  in cirrusfb_set_par_foo()
775 	vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);  in cirrusfb_set_par_foo()
793 	vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);  in cirrusfb_set_par_foo()
801 	vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);  in cirrusfb_set_par_foo()
804 	vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);  in cirrusfb_set_par_foo()
807 	vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);  in cirrusfb_set_par_foo()
810 	vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);  in cirrusfb_set_par_foo()
813 	vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);  in cirrusfb_set_par_foo()
816 	vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);  in cirrusfb_set_par_foo()
819 	vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);  in cirrusfb_set_par_foo()
834 	vga_wcrt(regbase, CL_CRT1A, tmp);  in cirrusfb_set_par_foo()
896 			vga_wseq(regbase, CL_SEQRE, tmp);  in cirrusfb_set_par_foo()
897 			vga_wseq(regbase, CL_SEQR1E, nom);  in cirrusfb_set_par_foo()
899 			vga_wseq(regbase, CL_SEQRE, nom);  in cirrusfb_set_par_foo()
900 			vga_wseq(regbase, CL_SEQR1E, tmp);  in cirrusfb_set_par_foo()
906 		vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);  in cirrusfb_set_par_foo()
910 		vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);  in cirrusfb_set_par_foo()
915 		vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);  in cirrusfb_set_par_foo()
917 		vga_wcrt(regbase, VGA_CRTC_REGS, 0x00);	/* interlace control */  in cirrusfb_set_par_foo()
929 	vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);  in cirrusfb_set_par_foo()
931 	vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);  in cirrusfb_set_par_foo()
942 		vga_wgfx(regbase, VGA_GFX_MODE, 0);	/* mode register */  in cirrusfb_set_par_foo()
953 			vga_wseq(regbase, CL_SEQR7,  in cirrusfb_set_par_foo()
960 			vga_wseq(regbase, CL_SEQR7,  in cirrusfb_set_par_foo()
961 				vga_rseq(regbase, CL_SEQR7) & ~0x01);  in cirrusfb_set_par_foo()
975 			vga_wseq(regbase, CL_SEQRF, 0xb0);  in cirrusfb_set_par_foo()
980 			vga_wseq(regbase, CL_SEQRF, 0xd0);  in cirrusfb_set_par_foo()
1006 		vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);  in cirrusfb_set_par_foo()
1008 		vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);  in cirrusfb_set_par_foo()
1027 			vga_wseq(regbase, CL_SEQR7,  in cirrusfb_set_par_foo()
1034 			vga_wseq(regbase, CL_SEQR7,  in cirrusfb_set_par_foo()
1035 				vga_rseq(regbase, CL_SEQR7) | 0x01);  in cirrusfb_set_par_foo()
1049 			vga_wseq(regbase, CL_SEQRF, 0xb0);  in cirrusfb_set_par_foo()
1055 			vga_wseq(regbase, CL_SEQRF, 0xb8);  in cirrusfb_set_par_foo()
1071 		vga_wgfx(regbase, VGA_GFX_MODE, 64);  in cirrusfb_set_par_foo()
1091 			vga_wseq(regbase, CL_SEQR7, 0x87);  in cirrusfb_set_par_foo()
1093 			vga_wseq(regbase, CL_SEQRF, 0xb0);  in cirrusfb_set_par_foo()
1097 			vga_wseq(regbase, CL_SEQR7, 0x27);  in cirrusfb_set_par_foo()
1099 			vga_wseq(regbase, CL_SEQRF, 0xb0);  in cirrusfb_set_par_foo()
1106 			vga_wseq(regbase, CL_SEQR7,  in cirrusfb_set_par_foo()
1111 			vga_wseq(regbase, CL_SEQR7, 0x17);  in cirrusfb_set_par_foo()
1117 			vga_wseq(regbase, CL_SEQR7,  in cirrusfb_set_par_foo()
1118 				vga_rseq(regbase, CL_SEQR7) & ~0x01);  in cirrusfb_set_par_foo()
1130 		vga_wgfx(regbase, VGA_GFX_MODE, 64);  in cirrusfb_set_par_foo()
1150 			vga_wseq(regbase, CL_SEQR7, 0x85);  in cirrusfb_set_par_foo()
1152 			vga_wseq(regbase, CL_SEQRF, 0xb0);  in cirrusfb_set_par_foo()
1156 			vga_wseq(regbase, CL_SEQR7, 0x25);  in cirrusfb_set_par_foo()
1158 			vga_wseq(regbase, CL_SEQRF, 0xb0);  in cirrusfb_set_par_foo()
1165 			vga_wseq(regbase, CL_SEQR7, 0xa5);  in cirrusfb_set_par_foo()
1169 			vga_wseq(regbase, CL_SEQR7, 0x15);  in cirrusfb_set_par_foo()
1175 			vga_wseq(regbase, CL_SEQR7,  in cirrusfb_set_par_foo()
1176 				vga_rseq(regbase, CL_SEQR7) & ~0x01);  in cirrusfb_set_par_foo()
1188 		vga_wgfx(regbase, VGA_GFX_MODE, 64);  in cirrusfb_set_par_foo()
1205 	vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff);  in cirrusfb_set_par_foo()
1211 	vga_wcrt(regbase, CL_CRT1B, tmp);  in cirrusfb_set_par_foo()
1215 		vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);  in cirrusfb_set_par_foo()
1232 		vga_wcrt(regbase, CL_CRT1E, tmp);  in cirrusfb_set_par_foo()
1237 	vga_wattr(regbase, CL_AR33, 0);  in cirrusfb_set_par_foo()
1258 	vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);  in cirrusfb_set_par_foo()
1339 		cirrusfb_WaitBLT(cinfo->regbase);  in cirrusfb_pan_display()
1342 	vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);  in cirrusfb_pan_display()
1343 	vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);  in cirrusfb_pan_display()
1346 	tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;  in cirrusfb_pan_display()
1355 	vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);  in cirrusfb_pan_display()
1359 		tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);  in cirrusfb_pan_display()
1364 		vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);  in cirrusfb_pan_display()
1372 		vga_wattr(cinfo->regbase, CL_AR33, xpix);  in cirrusfb_pan_display()
1411 	val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;  in cirrusfb_blank()
1412 	vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);  in cirrusfb_blank()
1433 	vga_wgfx(cinfo->regbase, CL_GRE, val);  in cirrusfb_blank()
1476 		vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);  in init_vgachip()
1479 		vga_wgfx(cinfo->regbase, CL_GR31, 0x00);  in init_vgachip()
1482 		vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);  in init_vgachip()
1485 		vga_wgfx(cinfo->regbase, CL_GR33, 0x00);  in init_vgachip()
1514 		vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);  in init_vgachip()
1517 		vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);  in init_vgachip()
1522 		vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);  in init_vgachip()
1526 			vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);  in init_vgachip()
1534 			vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);  in init_vgachip()
1538 			vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);  in init_vgachip()
1539 			vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);  in init_vgachip()
1544 	vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);  in init_vgachip()
1546 	vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);  in init_vgachip()
1548 	vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);  in init_vgachip()
1552 		vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);  in init_vgachip()
1558 	vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);  in init_vgachip()
1560 	vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);  in init_vgachip()
1562 	vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);  in init_vgachip()
1564 	vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);  in init_vgachip()
1569 		vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);  in init_vgachip()
1571 		vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);  in init_vgachip()
1575 	vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);  in init_vgachip()
1577 	vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);  in init_vgachip()
1579 	vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);  in init_vgachip()
1581 	vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);  in init_vgachip()
1583 	vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);  in init_vgachip()
1586 	vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);  in init_vgachip()
1589 	vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);  in init_vgachip()
1592 	vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);  in init_vgachip()
1594 	vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);  in init_vgachip()
1596 	vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);  in init_vgachip()
1598 	vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);  in init_vgachip()
1600 	vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);  in init_vgachip()
1602 	vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);  in init_vgachip()
1604 	vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);  in init_vgachip()
1606 	vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);  in init_vgachip()
1608 	vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);  in init_vgachip()
1613 		vga_wgfx(cinfo->regbase, CL_GRB, 0x20);  in init_vgachip()
1618 		vga_wgfx(cinfo->regbase, CL_GRB, 0x28);  in init_vgachip()
1620 	vga_wgfx(cinfo->regbase, CL_GRC, 0xff);	/* Color Key compare: - */  in init_vgachip()
1621 	vga_wgfx(cinfo->regbase, CL_GRD, 0x00);	/* Color Key compare mask: - */  in init_vgachip()
1622 	vga_wgfx(cinfo->regbase, CL_GRE, 0x00);	/* Miscellaneous control: - */  in init_vgachip()
1628 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);  in init_vgachip()
1629 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);  in init_vgachip()
1630 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);  in init_vgachip()
1631 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);  in init_vgachip()
1632 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);  in init_vgachip()
1633 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);  in init_vgachip()
1634 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);  in init_vgachip()
1635 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);  in init_vgachip()
1636 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);  in init_vgachip()
1637 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);  in init_vgachip()
1638 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);  in init_vgachip()
1639 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);  in init_vgachip()
1640 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);  in init_vgachip()
1641 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);  in init_vgachip()
1642 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);  in init_vgachip()
1643 	vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);  in init_vgachip()
1646 	vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);  in init_vgachip()
1648 	vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);  in init_vgachip()
1650 	vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);  in init_vgachip()
1652 	vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);  in init_vgachip()
1657 	vga_wgfx(cinfo->regbase, CL_GR31, 0x04);  in init_vgachip()
1659 	vga_wgfx(cinfo->regbase, CL_GR31, 0x00);  in init_vgachip()
1722 		while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03)  in cirrusfb_sync()
1759 	cirrusfb_RectFill(cinfo->regbase,  in cirrusfb_fillrect()
1800 	cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,  in cirrusfb_copyarea()
1836 			cirrusfb_RectFill(cinfo->regbase,  in cirrusfb_imageblit()
1844 		cirrusfb_RectFill(cinfo->regbase,  in cirrusfb_imageblit()
1862 					 u8 __iomem *regbase)  in cirrusfb_get_memsize()  argument
1868 		unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);  in cirrusfb_get_memsize()
1872 		unsigned char SRF = vga_rseq(regbase, CL_SEQRF);  in cirrusfb_get_memsize()
1950 		iounmap(cinfo->regbase);  in cirrusfb_zorro_unmap()
2112 	cinfo->regbase = NULL;  in cirrusfb_pci_register()
2119 		32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);  in cirrusfb_pci_register()
2203 	unsigned long regbase, ramsize, rambase;  in cirrusfb_zorro_register()  local
2214 	regbase = zorro_resource_start(z) + zcl->regoffset;  in cirrusfb_zorro_register()
2245 		 cirrusfb_board_info[btype].name, regbase, ramsize / MB_,  in cirrusfb_zorro_register()
2257 	info->fix.mmio_start = regbase;  in cirrusfb_zorro_register()
2258 	cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024)  in cirrusfb_zorro_register()
2259 					    : ZTWO_VADDR(regbase);  in cirrusfb_zorro_register()
2260 	if (!cinfo->regbase) {  in cirrusfb_zorro_register()
2284 		vga_wseq(cinfo->regbase, CL_SEQR1F,  in cirrusfb_zorro_register()
2302 	if (regbase > 16 * MB_)  in cirrusfb_zorro_register()
2303 		iounmap(cinfo->regbase);  in cirrusfb_zorro_register()
2421 	vga_w(cinfo->regbase, regofs + regnum, val);  in WGen()
2437 	return vga_r(cinfo->regbase, regofs + regnum);  in RGen()
2445 	if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {  in AttrOn()
2448 		vga_w(cinfo->regbase, VGA_ATT_IW,  in AttrOn()
2449 		      vga_r(cinfo->regbase, VGA_ATT_R));  in AttrOn()
2453 	vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);  in AttrOn()
2456 	vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);  in AttrOn()
2510 	assert(cinfo->regbase != NULL);  in WSFR()
2512 	z_writeb(val, cinfo->regbase + 0x8000);  in WSFR()
2522 	assert(cinfo->regbase != NULL);  in WSFR2()
2524 	z_writeb(val, cinfo->regbase + 0x9000);  in WSFR2()
2535 	vga_w(cinfo->regbase, VGA_PEL_IW, regnum);  in WClut()
2543 		vga_w(cinfo->regbase, data, red);  in WClut()
2544 		vga_w(cinfo->regbase, data, green);  in WClut()
2545 		vga_w(cinfo->regbase, data, blue);  in WClut()
2547 		vga_w(cinfo->regbase, data, blue);  in WClut()
2548 		vga_w(cinfo->regbase, data, green);  in WClut()
2549 		vga_w(cinfo->regbase, data, red);  in WClut()
2560 	vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2566 		*red = vga_r(cinfo->regbase, data);
2567 		*green = vga_r(cinfo->regbase, data);
2568 		*blue = vga_r(cinfo->regbase, data);
2570 		*blue = vga_r(cinfo->regbase, data);
2571 		*green = vga_r(cinfo->regbase, data);
2572 		*red = vga_r(cinfo->regbase, data);
2584 static void cirrusfb_WaitBLT(u8 __iomem *regbase)  in cirrusfb_WaitBLT()  argument
2586 	while (vga_rgfx(regbase, CL_GR31) & 0x08)  in cirrusfb_WaitBLT()
2596 static void cirrusfb_set_blitter(u8 __iomem *regbase,  in cirrusfb_set_blitter()  argument
2604 	vga_wgfx(regbase, CL_GR24, line_length & 0xff);  in cirrusfb_set_blitter()
2606 	vga_wgfx(regbase, CL_GR25, line_length >> 8);  in cirrusfb_set_blitter()
2608 	vga_wgfx(regbase, CL_GR26, line_length & 0xff);  in cirrusfb_set_blitter()
2610 	vga_wgfx(regbase, CL_GR27, line_length >> 8);  in cirrusfb_set_blitter()
2614 	vga_wgfx(regbase, CL_GR20, nwidth & 0xff);  in cirrusfb_set_blitter()
2616 	vga_wgfx(regbase, CL_GR21, nwidth >> 8);  in cirrusfb_set_blitter()
2620 	vga_wgfx(regbase, CL_GR22, nheight & 0xff);  in cirrusfb_set_blitter()
2622 	vga_wgfx(regbase, CL_GR23, nheight >> 8);  in cirrusfb_set_blitter()
2626 	vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));  in cirrusfb_set_blitter()
2628 	vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));  in cirrusfb_set_blitter()
2630 	vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));  in cirrusfb_set_blitter()
2634 	vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));  in cirrusfb_set_blitter()
2636 	vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));  in cirrusfb_set_blitter()
2638 	vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));  in cirrusfb_set_blitter()
2641 	vga_wgfx(regbase, CL_GR30, bltmode);	/* BLT mode */  in cirrusfb_set_blitter()
2644 	vga_wgfx(regbase, CL_GR32, 0x0d);	/* BLT ROP */  in cirrusfb_set_blitter()
2647 	vga_wgfx(regbase, CL_GR31, 0x02);	/* BLT Start/status */  in cirrusfb_set_blitter()
2656 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,  in cirrusfb_BitBLT()  argument
2688 	cirrusfb_WaitBLT(regbase);  in cirrusfb_BitBLT()
2690 	cirrusfb_set_blitter(regbase, nwidth, nheight,  in cirrusfb_BitBLT()
2700 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,  in cirrusfb_RectFill()  argument
2708 	cirrusfb_WaitBLT(regbase);  in cirrusfb_RectFill()
2712 	vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color);  in cirrusfb_RectFill()
2713 	vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color);  in cirrusfb_RectFill()
2717 		vga_wgfx(regbase, CL_GR10, bg_color >> 8);  in cirrusfb_RectFill()
2718 		vga_wgfx(regbase, CL_GR11, fg_color >> 8);  in cirrusfb_RectFill()
2722 		vga_wgfx(regbase, CL_GR12, bg_color >> 16);  in cirrusfb_RectFill()
2723 		vga_wgfx(regbase, CL_GR13, fg_color >> 16);  in cirrusfb_RectFill()
2727 		vga_wgfx(regbase, CL_GR14, bg_color >> 24);  in cirrusfb_RectFill()
2728 		vga_wgfx(regbase, CL_GR15, fg_color >> 24);  in cirrusfb_RectFill()
2731 	cirrusfb_set_blitter(regbase, width - 1, height - 1,  in cirrusfb_RectFill()
2816 				    caddr_t regbase,  in cirrusfb_dbg_print_regs()  argument
2832 			val = vga_rcrt(regbase, (unsigned char) reg);  in cirrusfb_dbg_print_regs()
2835 			val = vga_rseq(regbase, (unsigned char) reg);  in cirrusfb_dbg_print_regs()
2861 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase)  in cirrusfb_dbg_reg_dump()  argument
2865 	cirrusfb_dbg_print_regs(info, regbase, CRT,  in cirrusfb_dbg_reg_dump()
2919 	cirrusfb_dbg_print_regs(info, regbase, SEQ,  in cirrusfb_dbg_reg_dump()