Lines Matching refs:tmp
131 u32 tmp; in radeon_pm_disable_dynamic_mode() local
136 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
137 tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK; in radeon_pm_disable_dynamic_mode()
138 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK; in radeon_pm_disable_dynamic_mode()
139 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
141 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
142 tmp |= (MCLK_CNTL__FORCE_MCLKA | in radeon_pm_disable_dynamic_mode()
148 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
153 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
154 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_HDP | in radeon_pm_disable_dynamic_mode()
161 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
167 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_disable_dynamic_mode()
168 tmp |= (SCLK_CNTL2__R300_FORCE_TCL | in radeon_pm_disable_dynamic_mode()
171 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_pm_disable_dynamic_mode()
173 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
174 tmp |= (SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP | in radeon_pm_disable_dynamic_mode()
182 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
184 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_disable_dynamic_mode()
185 tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS | SCLK_MORE_CNTL__FORCE_MC_GUI | in radeon_pm_disable_dynamic_mode()
187 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
189 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
190 tmp |= (MCLK_CNTL__FORCE_MCLKA | in radeon_pm_disable_dynamic_mode()
195 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
197 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_disable_dynamic_mode()
198 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | in radeon_pm_disable_dynamic_mode()
201 OUTPLL(pllVCLK_ECP_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
203 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_disable_dynamic_mode()
204 tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | in radeon_pm_disable_dynamic_mode()
217 OUTPLL(pllPIXCLKS_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
225 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
226 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2); in radeon_pm_disable_dynamic_mode()
232 tmp |= SCLK_CNTL__FORCE_HDP| in radeon_pm_disable_dynamic_mode()
250 tmp |= SCLK_CNTL__FORCE_HDP | in radeon_pm_disable_dynamic_mode()
257 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
261 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_disable_dynamic_mode()
262 tmp |= SCLK_CNTL2__R300_FORCE_TCL | in radeon_pm_disable_dynamic_mode()
265 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_pm_disable_dynamic_mode()
269 tmp = INPLL(pllCLK_PIN_CNTL); in radeon_pm_disable_dynamic_mode()
270 tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL; in radeon_pm_disable_dynamic_mode()
271 OUTPLL(pllCLK_PIN_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
278 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
279 tmp &= ~(MCLK_CNTL__FORCE_MCLKA | in radeon_pm_disable_dynamic_mode()
281 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
286 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
287 tmp |= (MCLK_CNTL__FORCE_MCLKA | in radeon_pm_disable_dynamic_mode()
291 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
294 tmp = INPLL(pllMCLK_MISC); in radeon_pm_disable_dynamic_mode()
295 tmp &= ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT| in radeon_pm_disable_dynamic_mode()
299 OUTPLL(pllMCLK_MISC, tmp); in radeon_pm_disable_dynamic_mode()
304 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_disable_dynamic_mode()
305 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS| in radeon_pm_disable_dynamic_mode()
308 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
312 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_disable_dynamic_mode()
313 tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb | in radeon_pm_disable_dynamic_mode()
320 OUTPLL(pllPIXCLKS_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
323 tmp = INPLL( pllVCLK_ECP_CNTL); in radeon_pm_disable_dynamic_mode()
324 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | in radeon_pm_disable_dynamic_mode()
326 OUTPLL( pllVCLK_ECP_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
332 u32 tmp; in radeon_pm_enable_dynamic_mode() local
336 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
339 tmp &= ~(SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_RB); in radeon_pm_enable_dynamic_mode()
340 tmp &= ~(SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 | in radeon_pm_enable_dynamic_mode()
345 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
351 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_enable_dynamic_mode()
352 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL | in radeon_pm_enable_dynamic_mode()
355 tmp |= (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT | in radeon_pm_enable_dynamic_mode()
358 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_pm_enable_dynamic_mode()
360 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
361 tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP | in radeon_pm_enable_dynamic_mode()
369 tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK; in radeon_pm_enable_dynamic_mode()
370 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
372 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_enable_dynamic_mode()
373 tmp &= ~SCLK_MORE_CNTL__FORCEON; in radeon_pm_enable_dynamic_mode()
374 tmp |= SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT | in radeon_pm_enable_dynamic_mode()
377 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
379 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_enable_dynamic_mode()
380 tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | in radeon_pm_enable_dynamic_mode()
382 OUTPLL(pllVCLK_ECP_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
384 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_enable_dynamic_mode()
385 tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | in radeon_pm_enable_dynamic_mode()
398 OUTPLL(pllPIXCLKS_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
400 tmp = INPLL(pllMCLK_MISC); in radeon_pm_enable_dynamic_mode()
401 tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE | in radeon_pm_enable_dynamic_mode()
403 OUTPLL(pllMCLK_MISC, tmp); in radeon_pm_enable_dynamic_mode()
405 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_enable_dynamic_mode()
406 tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB); in radeon_pm_enable_dynamic_mode()
407 tmp &= ~(MCLK_CNTL__FORCE_YCLKA | in radeon_pm_enable_dynamic_mode()
416 if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) && in radeon_pm_enable_dynamic_mode()
417 (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) { in radeon_pm_enable_dynamic_mode()
419 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_enable_dynamic_mode()
422 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB; in radeon_pm_enable_dynamic_mode()
424 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA; in radeon_pm_enable_dynamic_mode()
426 tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA | in radeon_pm_enable_dynamic_mode()
430 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
436 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
437 tmp &= ~(SCLK_CNTL__R300_FORCE_VAP); in radeon_pm_enable_dynamic_mode()
438 tmp |= SCLK_CNTL__FORCE_CP; in radeon_pm_enable_dynamic_mode()
439 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
442 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_enable_dynamic_mode()
443 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL | in radeon_pm_enable_dynamic_mode()
446 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_pm_enable_dynamic_mode()
451 tmp = INPLL( pllCLK_PWRMGT_CNTL); in radeon_pm_enable_dynamic_mode()
452 tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK| in radeon_pm_enable_dynamic_mode()
455 tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK | in radeon_pm_enable_dynamic_mode()
457 OUTPLL( pllCLK_PWRMGT_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
460 tmp = INPLL(pllCLK_PIN_CNTL); in radeon_pm_enable_dynamic_mode()
461 tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL; in radeon_pm_enable_dynamic_mode()
462 OUTPLL(pllCLK_PIN_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
468 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
469 tmp &= ~SCLK_CNTL__FORCEON_MASK; in radeon_pm_enable_dynamic_mode()
476 tmp |= SCLK_CNTL__FORCE_CP; in radeon_pm_enable_dynamic_mode()
477 tmp |= SCLK_CNTL__FORCE_VIP; in radeon_pm_enable_dynamic_mode()
479 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
485 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_enable_dynamic_mode()
486 tmp &= ~SCLK_MORE_CNTL__FORCEON; in radeon_pm_enable_dynamic_mode()
492 tmp |= SCLK_MORE_CNTL__FORCEON; in radeon_pm_enable_dynamic_mode()
494 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
503 tmp = INPLL(pllPLL_PWRMGT_CNTL); in radeon_pm_enable_dynamic_mode()
504 tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE; in radeon_pm_enable_dynamic_mode()
505 OUTPLL(pllPLL_PWRMGT_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
509 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_enable_dynamic_mode()
510 tmp |= PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | in radeon_pm_enable_dynamic_mode()
517 OUTPLL(pllPIXCLKS_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
520 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_enable_dynamic_mode()
521 tmp |= VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | in radeon_pm_enable_dynamic_mode()
523 OUTPLL(pllVCLK_ECP_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
528 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_enable_dynamic_mode()
529 tmp &= ~(MCLK_CNTL__FORCE_MCLKA | in radeon_pm_enable_dynamic_mode()
533 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
536 tmp = INPLL(pllMCLK_MISC); in radeon_pm_enable_dynamic_mode()
537 tmp |= MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT| in radeon_pm_enable_dynamic_mode()
541 OUTPLL(pllMCLK_MISC, tmp); in radeon_pm_enable_dynamic_mode()
833 u32 tmp; in radeon_pm_setup_for_suspend() local
951 tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND; in radeon_pm_setup_for_suspend()
952 OUTPLL( pllMCLK_MISC, tmp); in radeon_pm_setup_for_suspend()
988 tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL; in radeon_pm_setup_for_suspend()
989 OUTPLL( pllPLL_PWRMGT_CNTL, tmp); in radeon_pm_setup_for_suspend()
1434 u32 tmp, tmp2; in radeon_pm_reset_pad_ctlr_strength() local
1440 tmp = INREG(PAD_CTLR_STRENGTH); in radeon_pm_reset_pad_ctlr_strength()
1444 if (tmp != tmp2) { in radeon_pm_reset_pad_ctlr_strength()
1445 tmp = tmp2; in radeon_pm_reset_pad_ctlr_strength()
1459 u32 tmp; in radeon_pm_all_ppls_off() local
1461 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_all_ppls_off()
1462 OUTPLL(pllPPLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1463 tmp = INPLL(pllP2PLL_CNTL); in radeon_pm_all_ppls_off()
1464 OUTPLL(pllP2PLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1465 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_all_ppls_off()
1466 OUTPLL(pllSPLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1467 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_all_ppls_off()
1468 OUTPLL(pllMPLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1473 u32 tmp; in radeon_pm_start_mclk_sclk() local
1476 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_start_mclk_sclk()
1477 OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK); in radeon_pm_start_mclk_sclk()
1480 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1483 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); in radeon_pm_start_mclk_sclk()
1487 tmp = INPLL(pllM_SPLL_REF_FB_DIV); in radeon_pm_start_mclk_sclk()
1488 tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul); in radeon_pm_start_mclk_sclk()
1489 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp); in radeon_pm_start_mclk_sclk()
1492 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1493 OUTPLL(pllSPLL_CNTL, tmp & ~1); in radeon_pm_start_mclk_sclk()
1499 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1500 OUTPLL(pllSPLL_CNTL, tmp & ~0x2); in radeon_pm_start_mclk_sclk()
1506 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_start_mclk_sclk()
1507 tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK; in radeon_pm_start_mclk_sclk()
1508 tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK; in radeon_pm_start_mclk_sclk()
1509 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_start_mclk_sclk()
1515 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1518 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); in radeon_pm_start_mclk_sclk()
1522 tmp = INPLL(pllM_SPLL_REF_FB_DIV); in radeon_pm_start_mclk_sclk()
1523 tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul); in radeon_pm_start_mclk_sclk()
1525 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp); in radeon_pm_start_mclk_sclk()
1527 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1528 OUTPLL(pllMPLL_CNTL, tmp & ~0x2); in radeon_pm_start_mclk_sclk()
1534 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1535 OUTPLL(pllMPLL_CNTL, tmp & ~0x1); in radeon_pm_start_mclk_sclk()
1541 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_start_mclk_sclk()
1542 tmp |= rinfo->save_regs[2] & 0xffff; in radeon_pm_start_mclk_sclk()
1543 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_start_mclk_sclk()
1580 u32 r2ec, tmp; in radeon_pm_m10_enable_lvds_spread_spectrum() local
1596 tmp = INPLL(pllSSPLL_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1597 OUTPLL(pllSSPLL_CNTL, tmp & ~0x2); in radeon_pm_m10_enable_lvds_spread_spectrum()
1599 tmp = INPLL(pllSSPLL_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1600 OUTPLL(pllSSPLL_CNTL, tmp & ~0x1); in radeon_pm_m10_enable_lvds_spread_spectrum()
1610 tmp = INREG(LVDS_GEN_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1611 OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN); in radeon_pm_m10_enable_lvds_spread_spectrum()
1614 tmp = INREG(LVDS_PLL_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1615 tmp &= ~0x30000; in radeon_pm_m10_enable_lvds_spread_spectrum()
1616 tmp |= 0x10000; in radeon_pm_m10_enable_lvds_spread_spectrum()
1617 OUTREG(LVDS_PLL_CNTL, tmp); in radeon_pm_m10_enable_lvds_spread_spectrum()
1628 tmp = INPLL(pllSS_TST_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1629 tmp |= 0x00400000; in radeon_pm_m10_enable_lvds_spread_spectrum()
1630 OUTPLL(pllSS_TST_CNTL, tmp); in radeon_pm_m10_enable_lvds_spread_spectrum()
1635 u32 tmp; in radeon_pm_restore_pixel_pll() local
1642 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_restore_pixel_pll()
1643 OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80); in radeon_pm_restore_pixel_pll()
1646 tmp = INPLL(pllPPLL_REF_DIV); in radeon_pm_restore_pixel_pll()
1647 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; in radeon_pm_restore_pixel_pll()
1648 OUTPLL(pllPPLL_REF_DIV, tmp); in radeon_pm_restore_pixel_pll()
1654 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_restore_pixel_pll()
1657 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); in radeon_pm_restore_pixel_pll()
1665 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_restore_pixel_pll()
1666 OUTPLL(pllPPLL_CNTL, tmp & ~0x2); in radeon_pm_restore_pixel_pll()
1669 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_restore_pixel_pll()
1670 OUTPLL(pllPPLL_CNTL, tmp & ~0x1); in radeon_pm_restore_pixel_pll()
1673 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_restore_pixel_pll()
1674 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3); in radeon_pm_restore_pixel_pll()
1677 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_restore_pixel_pll()
1678 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3); in radeon_pm_restore_pixel_pll()
1722 u32 tmp, i; in radeon_reinitialize_M10() local
1759 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; in radeon_reinitialize_M10()
1760 tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT; in radeon_reinitialize_M10()
1761 OUTREG(TV_DAC_CNTL, tmp); in radeon_reinitialize_M10()
1763 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; in radeon_reinitialize_M10()
1764 tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT; in radeon_reinitialize_M10()
1765 OUTREG(TV_DAC_CNTL, tmp); in radeon_reinitialize_M10()
1773 tmp = rinfo->save_regs[1] in radeon_reinitialize_M10()
1776 OUTPLL(pllCLK_PWRMGT_CNTL, tmp); in radeon_reinitialize_M10()
1803 tmp = rinfo->save_regs[2] & 0xff000000; in radeon_reinitialize_M10()
1804 tmp |= MCLK_CNTL__FORCE_MCLKA | in radeon_reinitialize_M10()
1809 OUTPLL(pllMCLK_CNTL, tmp); in radeon_reinitialize_M10()
1812 tmp = INPLL(pllSCLK_CNTL); in radeon_reinitialize_M10()
1813 tmp |= SCLK_CNTL__FORCE_DISP2| in radeon_reinitialize_M10()
1829 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | in radeon_reinitialize_M10()
1841 OUTPLL(pllSCLK_CNTL, tmp); in radeon_reinitialize_M10()
1879 tmp = INPLL(pllSCLK_CNTL2); /* What for ? */ in radeon_reinitialize_M10()
1880 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_reinitialize_M10()
1882 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_reinitialize_M10()
1883 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS | /* a guess */ in radeon_reinitialize_M10()
1886 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_reinitialize_M10()
1976 u32 tmp, i; in radeon_reinitialize_M9P() local
2010 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; in radeon_reinitialize_M9P()
2011 tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT; in radeon_reinitialize_M9P()
2012 OUTREG(TV_DAC_CNTL, tmp); in radeon_reinitialize_M9P()
2014 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; in radeon_reinitialize_M9P()
2015 tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT; in radeon_reinitialize_M9P()
2016 OUTREG(TV_DAC_CNTL, tmp); in radeon_reinitialize_M9P()
2028 tmp = rinfo->save_regs[1] in radeon_reinitialize_M9P()
2031 OUTPLL(pllCLK_PWRMGT_CNTL, tmp); in radeon_reinitialize_M9P()
2043 tmp = rinfo->save_regs[2] & 0xff000000; in radeon_reinitialize_M9P()
2044 tmp |= MCLK_CNTL__FORCE_MCLKA | in radeon_reinitialize_M9P()
2050 OUTPLL(pllMCLK_CNTL, tmp); in radeon_reinitialize_M9P()
2053 tmp = 0 | in radeon_reinitialize_M9P()
2068 OUTPLL(pllSCLK_CNTL, tmp); in radeon_reinitialize_M9P()
2101 tmp = rinfo->save_regs[0]; in radeon_reinitialize_M9P()
2102 tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK; in radeon_reinitialize_M9P()
2103 tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK; in radeon_reinitialize_M9P()
2104 OUTPLL(PLL_PWRMGT_CNTL, tmp); in radeon_reinitialize_M9P()
2154 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; in radeon_reinitialize_M9P()
2155 tmp |= rinfo->save_regs[34] & 0xffff0000; in radeon_reinitialize_M9P()
2156 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS; in radeon_reinitialize_M9P()
2157 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_reinitialize_M9P()
2159 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; in radeon_reinitialize_M9P()
2160 tmp |= rinfo->save_regs[34] & 0xffff0000; in radeon_reinitialize_M9P()
2161 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS; in radeon_reinitialize_M9P()
2162 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_reinitialize_M9P()
2177 tmp = INPLL(pllSSPLL_CNTL); in radeon_reinitialize_M9P()
2178 tmp &= ~2; in radeon_reinitialize_M9P()
2179 OUTPLL(pllSSPLL_CNTL, tmp); in radeon_reinitialize_M9P()
2181 tmp &= ~1; in radeon_reinitialize_M9P()
2182 OUTPLL(pllSSPLL_CNTL, tmp); in radeon_reinitialize_M9P()
2184 tmp |= 3; in radeon_reinitialize_M9P()
2185 OUTPLL(pllSSPLL_CNTL, tmp); in radeon_reinitialize_M9P()
2215 u32 tmp, tmp2;
2252 tmp = INPLL(pllVCLK_ECP_CNTL);
2253 OUTPLL(pllVCLK_ECP_CNTL, tmp);
2254 tmp = INPLL(pllPIXCLKS_CNTL);
2255 OUTPLL(pllPIXCLKS_CNTL, tmp);
2269 tmp = INPLL(M_SPLL_REF_FB_DIV);
2270 OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2271 tmp = INPLL(M_SPLL_REF_FB_DIV);
2272 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2275 tmp = INPLL(MPLL_CNTL);
2278 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2281 tmp = INPLL(M_SPLL_REF_FB_DIV);
2282 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2284 tmp = INPLL(MPLL_CNTL);
2285 OUTPLL(MPLL_CNTL, tmp & ~0x2);
2287 tmp = INPLL(MPLL_CNTL);
2288 OUTPLL(MPLL_CNTL, tmp & ~0x1);
2298 tmp = INPLL(SPLL_CNTL);
2301 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2304 tmp = INPLL(M_SPLL_REF_FB_DIV);
2305 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2307 tmp = INPLL(SPLL_CNTL);
2308 OUTPLL(SPLL_CNTL, tmp & ~0x1);
2310 tmp = INPLL(SPLL_CNTL);
2311 OUTPLL(SPLL_CNTL, tmp & ~0x2);
2314 tmp = INPLL(SCLK_CNTL);
2315 OUTPLL(SCLK_CNTL, tmp | 2);
2377 tmp = INREG(FP_GEN_CNTL);
2378 tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200;
2379 OUTREG(FP_GEN_CNTL, tmp);
2381 tmp = INREG(DISP_OUTPUT_CNTL);
2382 tmp &= ~0x400;
2383 OUTREG(DISP_OUTPUT_CNTL, tmp);
2389 tmp = INPLL(MCLK_MISC);
2390 tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE;
2391 OUTPLL(MCLK_MISC, tmp);
2393 tmp = INPLL(SCLK_CNTL);
2394 OUTPLL(SCLK_CNTL, tmp);
2401 tmp = INPLL(VCLK_ECP_CNTL);
2402 OUTPLL(VCLK_ECP_CNTL, tmp);
2404 tmp = INPLL(PPLL_CNTL);
2405 OUTPLL(PPLL_CNTL, tmp);
2409 tmp = INREG(FP_GEN_CNTL);
2411 tmp |= 2;
2412 OUTREG(FP_GEN_CNTL, tmp);
2414 OUTREG(FP_GEN_CNTL, tmp);
2420 tmp = INREG(CRTC_MORE_CNTL);
2421 OUTREG(CRTC_MORE_CNTL, tmp);
2448 tmp = INPLL(PPLL_REF_DIV);
2449 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2450 OUTPLL(PPLL_REF_DIV, tmp);
2458 tmp = INREG(CLOCK_CNTL_INDEX);
2460 OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
2466 tmp = INPLL(PPLL_CNTL);
2467 OUTPLL(PPLL_CNTL, tmp & ~0x2);
2469 tmp = INPLL(PPLL_CNTL);
2470 OUTPLL(PPLL_CNTL, tmp & ~0x1);
2473 tmp = INPLL(VCLK_ECP_CNTL);
2474 OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2477 tmp = INPLL(VCLK_ECP_CNTL);
2478 OUTPLL(VCLK_ECP_CNTL, tmp);
2493 tmp = INREG(TMDS_TRANSMITTER_CNTL);
2495 tmp |= TMDS_PLL_EN;
2496 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2498 tmp &= ~TMDS_PLLRST;
2499 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2538 u32 tmp; in radeon_set_suspend() local
2578 tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET in radeon_set_suspend()
2580 OUTPLL( pllMDLL_CKO, tmp ); in radeon_set_suspend()