139 			OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
148                 OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
161                 OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
171                 OUTPLL(pllSCLK_CNTL2, tmp);  in radeon_pm_disable_dynamic_mode()
182                 OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
187                 OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
195                 OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
201                 OUTPLL(pllVCLK_ECP_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
217                 OUTPLL(pllPIXCLKS_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
257     	OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
265 		OUTPLL(pllSCLK_CNTL2, tmp);  in radeon_pm_disable_dynamic_mode()
271 	OUTPLL(pllCLK_PIN_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
281 		OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
291 		OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
299 		OUTPLL(pllMCLK_MISC, tmp);  in radeon_pm_disable_dynamic_mode()
308 		OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
320  	OUTPLL(pllPIXCLKS_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
326 	OUTPLL( pllVCLK_ECP_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
345                 OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
358 		OUTPLL(pllSCLK_CNTL2, tmp);  in radeon_pm_enable_dynamic_mode()
370 		OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
377 		OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
382 		OUTPLL(pllVCLK_ECP_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
398 		OUTPLL(pllPIXCLKS_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
403 		OUTPLL(pllMCLK_MISC, tmp);  in radeon_pm_enable_dynamic_mode()
430 		OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
439 		OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
446 		OUTPLL(pllSCLK_CNTL2, tmp);  in radeon_pm_enable_dynamic_mode()
457 	OUTPLL( pllCLK_PWRMGT_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
462 	OUTPLL(pllCLK_PIN_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
479 	OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
494 		OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
505 		OUTPLL(pllPLL_PWRMGT_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
517 	OUTPLL(pllPIXCLKS_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
523 	OUTPLL(pllVCLK_ECP_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
533 		OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
541 		OUTPLL(pllMCLK_MISC, tmp);  in radeon_pm_enable_dynamic_mode()
689 	OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */  in radeon_pm_restore_regs()
691 	OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);  in radeon_pm_restore_regs()
692 	OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);  in radeon_pm_restore_regs()
693 	OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);  in radeon_pm_restore_regs()
694 	OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);  in radeon_pm_restore_regs()
695 	OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);  in radeon_pm_restore_regs()
696 	OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);  in radeon_pm_restore_regs()
697 	OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);  in radeon_pm_restore_regs()
698 	OUTPLL(MCLK_MISC, rinfo->save_regs[7]);  in radeon_pm_restore_regs()
700 		OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);  in radeon_pm_restore_regs()
719 	OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);  in radeon_pm_restore_regs()
751 		OUTPLL(pllPIXCLKS_CNTL,  in radeon_pm_program_v2clk()
755 		OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);  in radeon_pm_program_v2clk()
756 		OUTPLL(pllP2PLL_CNTL, 0x0000bf00);  in radeon_pm_program_v2clk()
758 		OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);  in radeon_pm_program_v2clk()
760 		OUTPLL(pllP2PLL_CNTL, 0x0000a700);  in radeon_pm_program_v2clk()
763 	OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);  in radeon_pm_program_v2clk()
765 	OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);  in radeon_pm_program_v2clk()
768 	OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);  in radeon_pm_program_v2clk()
771   	OUTPLL(pllPIXCLKS_CNTL,  in radeon_pm_program_v2clk()
795 	OUTPLL(PLL_PWRMGT_CNTL, reg);  in radeon_pm_low_current()
871 	OUTPLL( pllSCLK_CNTL, sclk_cntl);  in radeon_pm_setup_for_suspend()
878 	OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);		  in radeon_pm_setup_for_suspend()
888     	OUTPLL( pllMCLK_CNTL, mclk_cntl);  in radeon_pm_setup_for_suspend()
895 	OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);  in radeon_pm_setup_for_suspend()
907  	OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);  in radeon_pm_setup_for_suspend()
922 	OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);  in radeon_pm_setup_for_suspend()
944 	OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);  in radeon_pm_setup_for_suspend()
952 	OUTPLL( pllMCLK_MISC, tmp);  in radeon_pm_setup_for_suspend()
979 	OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);  in radeon_pm_setup_for_suspend()
989 	OUTPLL( pllPLL_PWRMGT_CNTL, tmp);  in radeon_pm_setup_for_suspend()
1044 	OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);  in radeon_pm_setup_for_suspend()
1045 	OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);  in radeon_pm_setup_for_suspend()
1046 	OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);  in radeon_pm_setup_for_suspend()
1161 	OUTPLL(pllMDLL_CKO,   	cko);  in radeon_pm_enable_dll()
1162 	OUTPLL(pllMDLL_RDCKA,  	cka);  in radeon_pm_enable_dll()
1163 	OUTPLL(pllMDLL_RDCKB,	ckb);  in radeon_pm_enable_dll()
1168 	OUTPLL(pllMDLL_CKO, cko);  in radeon_pm_enable_dll()
1171 	OUTPLL(pllMDLL_CKO, cko);  in radeon_pm_enable_dll()
1175 	OUTPLL(pllMDLL_RDCKA, cka);  in radeon_pm_enable_dll()
1178 	OUTPLL(pllMDLL_RDCKA, cka);  in radeon_pm_enable_dll()
1182 	OUTPLL(pllMDLL_RDCKB, ckb);  in radeon_pm_enable_dll()
1185 	OUTPLL(pllMDLL_RDCKB, ckb);  in radeon_pm_enable_dll()
1232 	OUTPLL(pllMDLL_RDCKA, dll_value);  in radeon_pm_enable_dll_m10()
1236 	OUTPLL(pllMDLL_RDCKA, dll_value);  in radeon_pm_enable_dll_m10()
1462 	OUTPLL(pllPPLL_CNTL, tmp | 0x3);  in radeon_pm_all_ppls_off()
1464 	OUTPLL(pllP2PLL_CNTL, tmp | 0x3);  in radeon_pm_all_ppls_off()
1466 	OUTPLL(pllSPLL_CNTL, tmp | 0x3);  in radeon_pm_all_ppls_off()
1468 	OUTPLL(pllMPLL_CNTL, tmp | 0x3);  in radeon_pm_all_ppls_off()
1477 	OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK);  in radeon_pm_start_mclk_sclk()
1489 	OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);  in radeon_pm_start_mclk_sclk()
1493 	OUTPLL(pllSPLL_CNTL, tmp & ~1);  in radeon_pm_start_mclk_sclk()
1500 	OUTPLL(pllSPLL_CNTL, tmp & ~0x2);  in radeon_pm_start_mclk_sclk()
1509 	OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_start_mclk_sclk()
1525 	OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);  in radeon_pm_start_mclk_sclk()
1528 	OUTPLL(pllMPLL_CNTL, tmp & ~0x2);  in radeon_pm_start_mclk_sclk()
1535 	OUTPLL(pllMPLL_CNTL, tmp & ~0x1);  in radeon_pm_start_mclk_sclk()
1543 	OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_start_mclk_sclk()
1564 	OUTPLL(pllSSPLL_CNTL, 0xbf03);  in radeon_pm_m10_disable_spread_spectrum()
1567 	OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);  in radeon_pm_m10_disable_spread_spectrum()
1591 	OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1594 	OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1595 	OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1597 	OUTPLL(pllSSPLL_CNTL, tmp & ~0x2);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1600 	OUTPLL(pllSSPLL_CNTL, tmp & ~0x1);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1603        	OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1619 	OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1620 	OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1630 	OUTPLL(pllSS_TST_CNTL, tmp);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1643 	OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80);  in radeon_pm_restore_pixel_pll()
1648 	OUTPLL(pllPPLL_REF_DIV, tmp);  in radeon_pm_restore_pixel_pll()
1663 	OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);  in radeon_pm_restore_pixel_pll()
1666 	OUTPLL(pllPPLL_CNTL, tmp & ~0x2);  in radeon_pm_restore_pixel_pll()
1670 	OUTPLL(pllPPLL_CNTL, tmp & ~0x1);  in radeon_pm_restore_pixel_pll()
1674 	OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);  in radeon_pm_restore_pixel_pll()
1678 	OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);  in radeon_pm_restore_pixel_pll()
1776 	OUTPLL(pllCLK_PWRMGT_CNTL, tmp);  in radeon_reinitialize_M10()
1800 	OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);  in radeon_reinitialize_M10()
1809 	OUTPLL(pllMCLK_CNTL, tmp);  in radeon_reinitialize_M10()
1841 	OUTPLL(pllSCLK_CNTL, tmp);  in radeon_reinitialize_M10()
1843 	OUTPLL(pllVCLK_ECP_CNTL, 0);  in radeon_reinitialize_M10()
1844 	OUTPLL(pllPIXCLKS_CNTL, 0);  in radeon_reinitialize_M10()
1845 	OUTPLL(pllMCLK_MISC,  in radeon_reinitialize_M10()
1852 	OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);  in radeon_reinitialize_M10()
1853 	OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);  in radeon_reinitialize_M10()
1854 	OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);  in radeon_reinitialize_M10()
1857 	OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);  in radeon_reinitialize_M10()
1858 	OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);  in radeon_reinitialize_M10()
1859 	OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);  in radeon_reinitialize_M10()
1860 	OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);  in radeon_reinitialize_M10()
1866 	OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);  in radeon_reinitialize_M10()
1872 	OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);  in radeon_reinitialize_M10()
1875 	OUTPLL(pllHTOTAL_CNTL, 0);  in radeon_reinitialize_M10()
1876 	OUTPLL(pllHTOTAL2_CNTL, 0);  in radeon_reinitialize_M10()
1880 	OUTPLL(pllSCLK_CNTL2, tmp);  in radeon_reinitialize_M10()
1886 	OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_reinitialize_M10()
2018 	OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);  in radeon_reinitialize_M9P()
2031 	OUTPLL(pllCLK_PWRMGT_CNTL, tmp);  in radeon_reinitialize_M9P()
2040        	OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);  in radeon_reinitialize_M9P()
2050 	OUTPLL(pllMCLK_CNTL, tmp);  in radeon_reinitialize_M9P()
2068 	OUTPLL(pllSCLK_CNTL, tmp);  in radeon_reinitialize_M9P()
2071 	OUTPLL(pllVCLK_ECP_CNTL, 0);  in radeon_reinitialize_M9P()
2072 	OUTPLL(pllPIXCLKS_CNTL, 0);  in radeon_reinitialize_M9P()
2075 	OUTPLL(pllMCLK_MISC,  in radeon_reinitialize_M9P()
2082 	OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);  in radeon_reinitialize_M9P()
2083 	OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);  in radeon_reinitialize_M9P()
2084 	OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);  in radeon_reinitialize_M9P()
2087 	OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);  in radeon_reinitialize_M9P()
2088 	OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);  in radeon_reinitialize_M9P()
2091 	OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);  in radeon_reinitialize_M9P()
2092 	OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);  in radeon_reinitialize_M9P()
2095 	OUTPLL(pllMDLL_CKO, 0x9c009c);  in radeon_reinitialize_M9P()
2096 	OUTPLL(pllMDLL_RDCKA, 0x08830883);  in radeon_reinitialize_M9P()
2097 	OUTPLL(pllMDLL_RDCKB, 0x08830883);  in radeon_reinitialize_M9P()
2104 	OUTPLL(PLL_PWRMGT_CNTL,  tmp);  in radeon_reinitialize_M9P()
2107 	OUTPLL(pllHTOTAL_CNTL, 0);  in radeon_reinitialize_M9P()
2108 	OUTPLL(pllHTOTAL2_CNTL, 0);  in radeon_reinitialize_M9P()
2157 	OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_reinitialize_M9P()
2162 	OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_reinitialize_M9P()
2175 	OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);  in radeon_reinitialize_M9P()
2176 	OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);  in radeon_reinitialize_M9P()
2179 	OUTPLL(pllSSPLL_CNTL, tmp);  in radeon_reinitialize_M9P()
2182 	OUTPLL(pllSSPLL_CNTL, tmp);  in radeon_reinitialize_M9P()
2185 	OUTPLL(pllSSPLL_CNTL, tmp);  in radeon_reinitialize_M9P()
2188 	OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/  in radeon_reinitialize_M9P()
2192 	OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);  in radeon_reinitialize_M9P()
2193 	OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);  in radeon_reinitialize_M9P()
2253 	OUTPLL(pllVCLK_ECP_CNTL, tmp);
2255 	OUTPLL(pllPIXCLKS_CNTL, tmp);
2257 	OUTPLL(MCLK_CNTL, 0xaa3f0000);
2258 	OUTPLL(SCLK_CNTL, 0xffff0000);
2259 	OUTPLL(pllMPLL_AUX_CNTL, 6);
2260 	OUTPLL(pllSPLL_AUX_CNTL, 1);
2261 	OUTPLL(MDLL_CKO, 0x9f009f);
2262 	OUTPLL(MDLL_RDCKA, 0x830083);
2263 	OUTPLL(pllMDLL_RDCKB, 0x830083);
2264 	OUTPLL(PPLL_CNTL, 0xa433);
2265 	OUTPLL(P2PLL_CNTL, 0xa433);
2266 	OUTPLL(MPLL_CNTL, 0x0400a403);
2267 	OUTPLL(SPLL_CNTL, 0x0400a433);
2270 	OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2272 	OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2282 	OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2285 	OUTPLL(MPLL_CNTL, tmp & ~0x2);
2288 	OUTPLL(MPLL_CNTL, tmp & ~0x1);
2291 	OUTPLL(MCLK_CNTL, 0xaa3f1212);
2305 	OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2308 	OUTPLL(SPLL_CNTL, tmp & ~0x1);
2311 	OUTPLL(SPLL_CNTL, tmp & ~0x2);
2315 	OUTPLL(SCLK_CNTL, tmp | 2);
2323 	OUTPLL(pllMDLL_CKO, cko);
2326 	OUTPLL(pllMDLL_CKO, cko);
2330 	OUTPLL(pllMDLL_RDCKA, cka);
2333 	OUTPLL(pllMDLL_RDCKA, cka);
2337 	OUTPLL(pllMDLL_RDCKB, ckb);
2340 	OUTPLL(pllMDLL_RDCKB, ckb);
2354 	OUTPLL(pllHTOTAL_CNTL, 0);
2355 	OUTPLL(pllHTOTAL2_CNTL, 0);
2385 	OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2386 	OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2387 	OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2391 	OUTPLL(MCLK_MISC, tmp);
2394 	OUTPLL(SCLK_CNTL, tmp);
2402 	OUTPLL(VCLK_ECP_CNTL, tmp);
2405 	OUTPLL(PPLL_CNTL, tmp);
2450 	OUTPLL(PPLL_REF_DIV, tmp);
2464 	OUTPLL(PPLL_DIV_0, 0x48090);
2467 	OUTPLL(PPLL_CNTL, tmp & ~0x2);
2470 	OUTPLL(PPLL_CNTL, tmp & ~0x1);
2474 	OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2478 	OUTPLL(VCLK_ECP_CNTL, tmp);
2580 				OUTPLL( pllMDLL_CKO, tmp );  in radeon_set_suspend()