Lines Matching refs:panel_info
177 rinfo->panel_info.pwr_delay = 200; in radeon_get_panel_info_BIOS()
185 rinfo->panel_info.xres = BIOS_IN16(tmp + 25); in radeon_get_panel_info_BIOS()
186 rinfo->panel_info.yres = BIOS_IN16(tmp + 27); in radeon_get_panel_info_BIOS()
188 rinfo->panel_info.xres, rinfo->panel_info.yres); in radeon_get_panel_info_BIOS()
190 rinfo->panel_info.pwr_delay = BIOS_IN16(tmp + 44); in radeon_get_panel_info_BIOS()
191 pr_debug("BIOS provided panel power delay: %d\n", rinfo->panel_info.pwr_delay); in radeon_get_panel_info_BIOS()
192 if (rinfo->panel_info.pwr_delay > 2000 || rinfo->panel_info.pwr_delay <= 0) in radeon_get_panel_info_BIOS()
193 rinfo->panel_info.pwr_delay = 2000; in radeon_get_panel_info_BIOS()
198 rinfo->panel_info.ref_divider = BIOS_IN16(tmp + 46); in radeon_get_panel_info_BIOS()
199 rinfo->panel_info.post_divider = BIOS_IN8(tmp + 48); in radeon_get_panel_info_BIOS()
200 rinfo->panel_info.fbk_divider = BIOS_IN16(tmp + 49); in radeon_get_panel_info_BIOS()
201 if (rinfo->panel_info.ref_divider != 0 && in radeon_get_panel_info_BIOS()
202 rinfo->panel_info.fbk_divider > 3) { in radeon_get_panel_info_BIOS()
203 rinfo->panel_info.use_bios_dividers = 1; in radeon_get_panel_info_BIOS()
205 pr_debug("ref_divider = %x\n", rinfo->panel_info.ref_divider); in radeon_get_panel_info_BIOS()
206 pr_debug("post_divider = %x\n", rinfo->panel_info.post_divider); in radeon_get_panel_info_BIOS()
207 pr_debug("fbk_divider = %x\n", rinfo->panel_info.fbk_divider); in radeon_get_panel_info_BIOS()
215 if ((BIOS_IN16(tmp0) == rinfo->panel_info.xres) && in radeon_get_panel_info_BIOS()
216 (BIOS_IN16(tmp0+2) == rinfo->panel_info.yres)) { in radeon_get_panel_info_BIOS()
217 rinfo->panel_info.hblank = (BIOS_IN16(tmp0+17) - BIOS_IN16(tmp0+19)) * 8; in radeon_get_panel_info_BIOS()
218 rinfo->panel_info.hOver_plus = ((BIOS_IN16(tmp0+21) - in radeon_get_panel_info_BIOS()
220 rinfo->panel_info.hSync_width = BIOS_IN8(tmp0+23) * 8; in radeon_get_panel_info_BIOS()
221 rinfo->panel_info.vblank = BIOS_IN16(tmp0+24) - BIOS_IN16(tmp0+26); in radeon_get_panel_info_BIOS()
222 rinfo->panel_info.vOver_plus = (BIOS_IN16(tmp0+28) & 0x7ff) - BIOS_IN16(tmp0+26); in radeon_get_panel_info_BIOS()
223 rinfo->panel_info.vSync_width = (BIOS_IN16(tmp0+28) & 0xf800) >> 11; in radeon_get_panel_info_BIOS()
224 rinfo->panel_info.clock = BIOS_IN16(tmp0+9); in radeon_get_panel_info_BIOS()
228 rinfo->panel_info.hAct_high = 1; in radeon_get_panel_info_BIOS()
229 rinfo->panel_info.vAct_high = 1; in radeon_get_panel_info_BIOS()
231 rinfo->panel_info.valid = 1; in radeon_get_panel_info_BIOS()
234 pr_debug(" hblank: %d\n", rinfo->panel_info.hblank); in radeon_get_panel_info_BIOS()
235 pr_debug(" hOver_plus: %d\n", rinfo->panel_info.hOver_plus); in radeon_get_panel_info_BIOS()
236 pr_debug(" hSync_width: %d\n", rinfo->panel_info.hSync_width); in radeon_get_panel_info_BIOS()
237 pr_debug(" vblank: %d\n", rinfo->panel_info.vblank); in radeon_get_panel_info_BIOS()
238 pr_debug(" vOver_plus: %d\n", rinfo->panel_info.vOver_plus); in radeon_get_panel_info_BIOS()
239 pr_debug(" vSync_width: %d\n", rinfo->panel_info.vSync_width); in radeon_get_panel_info_BIOS()
240 pr_debug(" clock: %d\n", rinfo->panel_info.clock); in radeon_get_panel_info_BIOS()
661 if (!rinfo->panel_info.use_bios_dividers && rinfo->mon1_type == MT_LCD in radeon_fixup_panel_info()
668 rinfo->panel_info.ref_divider = rinfo->pll.ref_div; in radeon_fixup_panel_info()
669 rinfo->panel_info.fbk_divider = ppll_divn & 0x7ff; in radeon_fixup_panel_info()
670 rinfo->panel_info.post_divider = (ppll_divn >> 16) & 0x7; in radeon_fixup_panel_info()
671 rinfo->panel_info.use_bios_dividers = 1; in radeon_fixup_panel_info()
675 rinfo->panel_info.fbk_divider | in radeon_fixup_panel_info()
676 (rinfo->panel_info.post_divider << 16), in radeon_fixup_panel_info()
689 rinfo->panel_info.xres = var->xres; in radeon_var_to_panel_info()
690 rinfo->panel_info.yres = var->yres; in radeon_var_to_panel_info()
691 rinfo->panel_info.clock = 100000000 / var->pixclock; in radeon_var_to_panel_info()
692 rinfo->panel_info.hOver_plus = var->right_margin; in radeon_var_to_panel_info()
693 rinfo->panel_info.hSync_width = var->hsync_len; in radeon_var_to_panel_info()
694 rinfo->panel_info.hblank = var->left_margin + in radeon_var_to_panel_info()
696 rinfo->panel_info.vOver_plus = var->lower_margin; in radeon_var_to_panel_info()
697 rinfo->panel_info.vSync_width = var->vsync_len; in radeon_var_to_panel_info()
698 rinfo->panel_info.vblank = var->upper_margin + in radeon_var_to_panel_info()
700 rinfo->panel_info.hAct_high = in radeon_var_to_panel_info()
702 rinfo->panel_info.vAct_high = in radeon_var_to_panel_info()
704 rinfo->panel_info.valid = 1; in radeon_var_to_panel_info()
710 rinfo->panel_info.pwr_delay = 200; in radeon_var_to_panel_info()
778 if (!rinfo->panel_info.use_bios_dividers && rinfo->mon1_type != MT_CRT in radeon_check_modes()
783 if (var.xres >= rinfo->panel_info.xres && in radeon_check_modes()
784 var.yres >= rinfo->panel_info.yres) in radeon_check_modes()
798 if (rinfo->mon1_type != MT_CRT && rinfo->panel_info.valid) { in radeon_check_modes()
802 var->xres = rinfo->panel_info.xres; in radeon_check_modes()
803 var->yres = rinfo->panel_info.yres; in radeon_check_modes()
804 var->xres_virtual = rinfo->panel_info.xres; in radeon_check_modes()
805 var->yres_virtual = rinfo->panel_info.yres; in radeon_check_modes()
808 var->pixclock = 100000000 / rinfo->panel_info.clock; in radeon_check_modes()
809 var->left_margin = (rinfo->panel_info.hblank - rinfo->panel_info.hOver_plus in radeon_check_modes()
810 - rinfo->panel_info.hSync_width); in radeon_check_modes()
811 var->right_margin = rinfo->panel_info.hOver_plus; in radeon_check_modes()
812 var->upper_margin = (rinfo->panel_info.vblank - rinfo->panel_info.vOver_plus in radeon_check_modes()
813 - rinfo->panel_info.vSync_width); in radeon_check_modes()
814 var->lower_margin = rinfo->panel_info.vOver_plus; in radeon_check_modes()
815 var->hsync_len = rinfo->panel_info.hSync_width; in radeon_check_modes()
816 var->vsync_len = rinfo->panel_info.vSync_width; in radeon_check_modes()
818 if (rinfo->panel_info.hAct_high) in radeon_check_modes()
820 if (rinfo->panel_info.vAct_high) in radeon_check_modes()
844 if (rinfo->mon1_type != MT_CRT && !rinfo->panel_info.valid) { in radeon_check_modes()
850 if (rinfo->panel_info.xres == 0 || rinfo->panel_info.yres == 0) { in radeon_check_modes()
852 rinfo->panel_info.xres = ((tmp >> HORZ_PANEL_SHIFT) + 1) * 8; in radeon_check_modes()
854 rinfo->panel_info.yres = (tmp >> VERT_PANEL_SHIFT) + 1; in radeon_check_modes()
856 if (rinfo->panel_info.xres == 0 || rinfo->panel_info.yres == 0) { in radeon_check_modes()
862 rinfo->panel_info.xres, rinfo->panel_info.yres); in radeon_check_modes()
865 snprintf(modename, 31, "%dx%d", rinfo->panel_info.xres, rinfo->panel_info.yres); in radeon_check_modes()