Lines Matching refs:par
42 static void aty_dac_waste4(const struct atyfb_par *par) in aty_dac_waste4() argument
44 (void) aty_ld_8(DAC_REGS, par); in aty_dac_waste4()
46 (void) aty_ld_8(DAC_REGS + 2, par); in aty_dac_waste4()
47 (void) aty_ld_8(DAC_REGS + 2, par); in aty_dac_waste4()
48 (void) aty_ld_8(DAC_REGS + 2, par); in aty_dac_waste4()
49 (void) aty_ld_8(DAC_REGS + 2, par); in aty_dac_waste4()
52 static void aty_StrobeClock(const struct atyfb_par *par) in aty_StrobeClock() argument
58 tmp = aty_ld_8(CLOCK_CNTL, par); in aty_StrobeClock()
59 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, tmp | CLOCK_STROBE, par); in aty_StrobeClock()
68 static void aty_st_514(int offset, u8 val, const struct atyfb_par *par) in aty_st_514() argument
70 aty_st_8(DAC_CNTL, 1, par); in aty_st_514()
72 aty_st_8(DAC_W_INDEX, offset & 0xff, par); in aty_st_514()
74 aty_st_8(DAC_DATA, (offset >> 8) & 0xff, par); in aty_st_514()
75 aty_st_8(DAC_MASK, val, par); in aty_st_514()
76 aty_st_8(DAC_CNTL, 0, par); in aty_st_514()
82 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_set_dac_514() local
111 aty_st_514(0x90, 0x00, par); /* VRAM Mask Low */ in aty_set_dac_514()
112 aty_st_514(0x04, tab[i].pixel_dly, par); /* Horizontal Sync Control */ in aty_set_dac_514()
113 aty_st_514(0x05, 0x00, par); /* Power Management */ in aty_set_dac_514()
114 aty_st_514(0x02, 0x01, par); /* Misc Clock Control */ in aty_set_dac_514()
115 aty_st_514(0x71, tab[i].misc2_cntl, par); /* Misc Control 2 */ in aty_set_dac_514()
116 aty_st_514(0x0a, tab[i].pixel_rep, par); /* Pixel Format */ in aty_set_dac_514()
117 aty_st_514(tab[i].pixel_cntl_index, tab[i].pixel_cntl_v1, par); in aty_set_dac_514()
163 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_pll_514_to_var() local
170 return ((par->ref_clk_per * ref_div_count) << (3 - df))/ in aty_pll_514_to_var()
177 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_set_pll_514() local
179 aty_st_514(0x06, 0x02, par); /* DAC Operation */ in aty_set_pll_514()
180 aty_st_514(0x10, 0x01, par); /* PLL Control 1 */ in aty_set_pll_514()
181 aty_st_514(0x70, 0x01, par); /* Misc Control 1 */ in aty_set_pll_514()
182 aty_st_514(0x8f, 0x1f, par); /* PLL Ref. Divider Input */ in aty_set_pll_514()
183 aty_st_514(0x03, 0x00, par); /* Sync Control */ in aty_set_pll_514()
184 aty_st_514(0x05, 0x00, par); /* Power Management */ in aty_set_pll_514()
185 aty_st_514(0x20, pll->ibm514.m, par); /* F0 / M0 */ in aty_set_pll_514()
186 aty_st_514(0x21, pll->ibm514.n, par); /* F1 / N0 */ in aty_set_pll_514()
208 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_set_dac_ATI68860_B() local
243 temp = aty_ld_8(DAC_CNTL, par); in aty_set_dac_ATI68860_B()
245 par); in aty_set_dac_ATI68860_B()
247 aty_st_8(DAC_REGS + 2, 0x1D, par); in aty_set_dac_ATI68860_B()
248 aty_st_8(DAC_REGS + 3, gModeReg, par); in aty_set_dac_ATI68860_B()
249 aty_st_8(DAC_REGS, 0x02, par); in aty_set_dac_ATI68860_B()
251 temp = aty_ld_8(DAC_CNTL, par); in aty_set_dac_ATI68860_B()
252 aty_st_8(DAC_CNTL, temp | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3, par); in aty_set_dac_ATI68860_B()
266 temp = aty_ld_8(DAC_REGS, par); in aty_set_dac_ATI68860_B()
268 par); in aty_set_dac_ATI68860_B()
269 temp = aty_ld_8(DAC_CNTL, par); in aty_set_dac_ATI68860_B()
271 par); in aty_set_dac_ATI68860_B()
273 aty_st_le32(BUS_CNTL, 0x890e20f1, par); in aty_set_dac_ATI68860_B()
274 aty_st_le32(DAC_CNTL, 0x47052100, par); in aty_set_dac_ATI68860_B()
291 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_set_dac_ATT21C498() local
323 aty_dac_waste4(par); in aty_set_dac_ATT21C498()
324 aty_st_8(DAC_REGS + 2, DACMask, par); in aty_set_dac_ATT21C498()
326 aty_st_le32(BUS_CNTL, 0x890e20f1, par); in aty_set_dac_ATT21C498()
327 aty_st_le32(DAC_CNTL, 0x00072000, par); in aty_set_dac_ATT21C498()
405 static void aty_ICS2595_put1bit(u8 data, const struct atyfb_par *par) in aty_ICS2595_put1bit() argument
410 tmp = aty_ld_8(CLOCK_CNTL, par); in aty_ICS2595_put1bit()
411 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, in aty_ICS2595_put1bit()
412 (tmp & ~0x04) | (data << 2), par); in aty_ICS2595_put1bit()
414 tmp = aty_ld_8(CLOCK_CNTL, par); in aty_ICS2595_put1bit()
415 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (0 << 3), in aty_ICS2595_put1bit()
416 par); in aty_ICS2595_put1bit()
418 aty_StrobeClock(par); in aty_ICS2595_put1bit()
420 tmp = aty_ld_8(CLOCK_CNTL, par); in aty_ICS2595_put1bit()
421 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (1 << 3), in aty_ICS2595_put1bit()
422 par); in aty_ICS2595_put1bit()
424 aty_StrobeClock(par); in aty_ICS2595_put1bit()
431 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_set_pll18818() local
440 old_clock_cntl = aty_ld_8(CLOCK_CNTL, par); in aty_set_pll18818()
441 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 0, par); in aty_set_pll18818()
443 old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par); in aty_set_pll18818()
445 old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par); in aty_set_pll18818()
453 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 0, par); /* Strobe = 0 */ in aty_set_pll18818()
454 aty_StrobeClock(par); in aty_set_pll18818()
455 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 1, par); /* Strobe = 0 */ in aty_set_pll18818()
456 aty_StrobeClock(par); in aty_set_pll18818()
458 aty_ICS2595_put1bit(1, par); /* Send start bits */ in aty_set_pll18818()
459 aty_ICS2595_put1bit(0, par); /* Start bit */ in aty_set_pll18818()
460 aty_ICS2595_put1bit(0, par); /* Read / ~Write */ in aty_set_pll18818()
463 aty_ICS2595_put1bit(locationAddr & 1, par); in aty_set_pll18818()
468 aty_ICS2595_put1bit(program_bits & 1, par); in aty_set_pll18818()
474 (void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */ in aty_set_pll18818()
475 aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par); in aty_set_pll18818()
476 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, in aty_set_pll18818()
477 old_clock_cntl | CLOCK_STROBE, par); in aty_set_pll18818()
480 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, in aty_set_pll18818()
481 ((pll->ics2595.locationAddr & 0x0F) | CLOCK_STROBE), par); in aty_set_pll18818()
574 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_set_pll_1703() local
580 old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par); in aty_set_pll_1703()
582 old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par); in aty_set_pll_1703()
588 aty_dac_waste4(par); in aty_set_pll_1703()
590 (void) aty_ld_8(DAC_REGS + 2, par); in aty_set_pll_1703()
591 aty_st_8(DAC_REGS + 2, (locationAddr << 1) + 0x20, par); in aty_set_pll_1703()
592 aty_st_8(DAC_REGS + 2, 0, par); in aty_set_pll_1703()
593 aty_st_8(DAC_REGS + 2, (program_bits & 0xFF00) >> 8, par); in aty_set_pll_1703()
594 aty_st_8(DAC_REGS + 2, (program_bits & 0xFF), par); in aty_set_pll_1703()
596 (void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */ in aty_set_pll_1703()
597 aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par); in aty_set_pll_1703()
693 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_set_pll_8398() local
700 old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par); in aty_set_pll_8398()
702 old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par); in aty_set_pll_8398()
708 tmp = aty_ld_8(DAC_CNTL, par); in aty_set_pll_8398()
709 aty_st_8(DAC_CNTL, tmp | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3, par); in aty_set_pll_8398()
711 aty_st_8(DAC_REGS, locationAddr, par); in aty_set_pll_8398()
712 aty_st_8(DAC_REGS + 1, (program_bits & 0xff00) >> 8, par); in aty_set_pll_8398()
713 aty_st_8(DAC_REGS + 1, (program_bits & 0xff), par); in aty_set_pll_8398()
715 tmp = aty_ld_8(DAC_CNTL, par); in aty_set_pll_8398()
717 par); in aty_set_pll_8398()
719 (void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */ in aty_set_pll_8398()
720 aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par); in aty_set_pll_8398()
811 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_set_pll_408() local
818 old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par); in aty_set_pll_408()
820 old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par); in aty_set_pll_408()
826 aty_dac_waste4(par); in aty_set_pll_408()
827 tmpB = aty_ld_8(DAC_REGS + 2, par) | 1; in aty_set_pll_408()
828 aty_dac_waste4(par); in aty_set_pll_408()
829 aty_st_8(DAC_REGS + 2, tmpB, par); in aty_set_pll_408()
836 aty_st_8(DAC_REGS, tmpB, par); in aty_set_pll_408()
837 aty_st_8(DAC_REGS + 2, tmpA, par); in aty_set_pll_408()
845 aty_st_8(DAC_REGS, tmpB, par); in aty_set_pll_408()
846 aty_st_8(DAC_REGS + 2, tmpA, par); in aty_set_pll_408()
851 aty_st_8(DAC_REGS, tmpB, par); in aty_set_pll_408()
852 aty_st_8(DAC_REGS + 2, tmpA, par); in aty_set_pll_408()
857 aty_st_8(DAC_REGS, tmpB, par); in aty_set_pll_408()
858 aty_st_8(DAC_REGS + 2, tmpA, par); in aty_set_pll_408()
864 aty_st_8(DAC_REGS, tmpB, par); in aty_set_pll_408()
865 aty_st_8(DAC_REGS + 2, tmpA, par); in aty_set_pll_408()
867 (void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */ in aty_set_pll_408()
868 aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par); in aty_set_pll_408()
887 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_set_dac_unsupported() local
889 aty_st_le32(BUS_CNTL, 0x890e20f1, par); in aty_set_dac_unsupported()
890 aty_st_le32(DAC_CNTL, 0x47052100, par); in aty_set_dac_unsupported()
892 aty_st_le32(BUS_CNTL, 0x590e10ff, par); in aty_set_dac_unsupported()
893 aty_st_le32(DAC_CNTL, 0x47012100, par); in aty_set_dac_unsupported()