Lines Matching defs:usb_dr_mmap

303 struct usb_dr_mmap {  struct
305 	u8 res1[256];
306 	u16 caplength;		/* Capability Register Length */
307 	u16 hciversion;		/* Host Controller Interface Version */
308 	u32 hcsparams;		/* Host Controller Structual Parameters */
309 	u32 hccparams;		/* Host Controller Capability Parameters */
310 	u8 res2[20];
311 	u32 dciversion;		/* Device Controller Interface Version */
312 	u32 dccparams;		/* Device Controller Capability Parameters */
313 	u8 res3[24];
315 	u32 usbcmd;		/* USB Command Register */
316 	u32 usbsts;		/* USB Status Register */
317 	u32 usbintr;		/* USB Interrupt Enable Register */
318 	u32 frindex;		/* Frame Index Register */
319 	u8 res4[4];
320 	u32 deviceaddr;		/* Device Address */
321 	u32 endpointlistaddr;	/* Endpoint List Address Register */
322 	u8 res5[4];
323 	u32 burstsize;		/* Master Interface Data Burst Size Register */
324 	u32 txttfilltuning;	/* Transmit FIFO Tuning Controls Register */
325 	u8 res6[8];
326 	u32 ulpiview;		/* ULPI register access */
327 	u8 res7[12];
328 	u32 configflag;		/* Configure Flag Register */
329 	u32 portsc;		/* Port 1 Status and Control Register */
330 	u8 res8[28];
331 	u32 otgsc;		/* On-The-Go Status and Control */
332 	u32 usbmode;		/* USB Mode Register */
333 	u32 endptsetupstat;	/* Endpoint Setup Status Register */
334 	u32 endpointprime;	/* Endpoint Initialization Register */
335 	u32 endptflush;		/* Endpoint Flush Register */
336 	u32 endptstatus;	/* Endpoint Status Register */
337 	u32 endptcomplete;	/* Endpoint Complete Register */
338 	u32 endptctrl[6];	/* Endpoint Control Registers */
339 	u8 res9[552];
340 	u32 snoop1;
341 	u32 snoop2;
342 	u32 age_cnt_thresh;	/* Age Count Threshold Register */
343 	u32 pri_ctrl;		/* Priority Control Register */
344 	u32 si_ctrl;		/* System Interface Control Register */
345 	u8 res10[236];
346 	u32 control;		/* General Purpose Control Register */