Lines Matching refs:TUSB_SYS_REG_BASE
25 #define TUSB_SYS_REG_BASE 0x800 macro
27 #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000)
33 #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004)
34 #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008)
58 #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c)
70 #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010)
73 #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014)
76 #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018)
81 #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c)
98 #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020)
99 #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028)
100 #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c)
116 #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030)
117 #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034)
118 #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038)
119 #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c)
120 #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040)
121 #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044)
122 #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048)
123 #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c)
124 #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050)
125 #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054)
126 #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058)
127 #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c)
128 #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060)
129 #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064)
130 #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068)
131 #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c)
134 #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070)
135 #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074)
136 #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078)
137 #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c)
174 #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080)
175 #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084)
176 #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100)
177 #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104)
178 #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108)
179 #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148)
186 #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8)
187 #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4)
188 #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8)
206 #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8)
207 #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc)