103 static void musb_ep_program(struct musb *musb, u8 epnum,
139 				ep->epnum, csr))  in musb_h_tx_flush_fifo()
161 			ep->epnum, csr);  in musb_h_ep0_flush_fifo()
176 	if (ep->epnum) {  in musb_h_tx_start()
230 	int			epnum = hw_ep->epnum;  in musb_start_urb()  local
258 			qh, urb, address, qh->epnum,  in musb_start_urb()
266 			epnum, buf + offset, len);  in musb_start_urb()
270 	musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);  in musb_start_urb()
294 			dev_dbg(musb->controller, "SOF for %d\n", epnum);  in musb_start_urb()
302 		dev_dbg(musb->controller, "Start TX%d %s\n", epnum,  in musb_start_urb()
349 	usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);  in musb_save_toggle()
439 		    hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));  in musb_advance_schedule()
467 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)  in musb_host_packet_rx()  argument
475 	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;  in musb_host_packet_rx()
483 	dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,  in musb_host_packet_rx()
568 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, u8 epnum)  in musb_rx_reinit()  argument
570 	struct musb_hw_ep *ep = musb->endpoints + epnum;  in musb_rx_reinit()
600 			WARNING("rx%d, packet/%d ready?\n", ep->epnum,  in musb_rx_reinit()
608 		musb_write_rxfunaddr(musb, epnum, qh->addr_reg);  in musb_rx_reinit()
609 		musb_write_rxhubaddr(musb, epnum, qh->h_addr_reg);  in musb_rx_reinit()
610 		musb_write_rxhubport(musb, epnum, qh->h_port_reg);  in musb_rx_reinit()
741 static void musb_ep_program(struct musb *musb, u8 epnum,  in musb_ep_program()  argument
749 	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;  in musb_ep_program()
759 			epnum, urb, urb->dev->speed,  in musb_ep_program()
760 			qh->addr_reg, qh->epnum, is_out ? "out" : "in",  in musb_ep_program()
764 	musb_ep_select(mbase, epnum);  in musb_ep_program()
776 	if (use_dma && is_dma_capable() && epnum && dma_controller) {  in musb_ep_program()
801 		musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));  in musb_ep_program()
804 		if (epnum) {  in musb_ep_program()
830 				if (usb_gettoggle(urb->dev, qh->epnum, 1))  in musb_ep_program()
849 			musb_write_txfunaddr(musb, epnum, qh->addr_reg);  in musb_ep_program()
850 			musb_write_txhubaddr(musb, epnum, qh->h_addr_reg);  in musb_ep_program()
851 			musb_write_txhubport(musb, epnum, qh->h_port_reg);  in musb_ep_program()
857 		if (epnum) {  in musb_ep_program()
923 			musb_rx_reinit(musb, qh, epnum);  in musb_ep_program()
926 			if (usb_gettoggle(urb->dev, qh->epnum, 0))  in musb_ep_program()
941 						hw_ep->epnum, csr);  in musb_ep_program()
975 		dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);  in musb_ep_program()
994 	musb_ep_select(mbase, ep->epnum);  in musb_bulk_nak_timeout()
1270 void musb_host_tx(struct musb *musb, u8 epnum)  in musb_host_tx()  argument
1277 	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;  in musb_host_tx()
1286 	musb_ep_select(mbase, epnum);  in musb_host_tx()
1291 		dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);  in musb_host_tx()
1297 	dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,  in musb_host_tx()
1303 		dev_dbg(musb->controller, "TX end %d stall\n", epnum);  in musb_host_tx()
1310 		dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);  in musb_host_tx()
1318 				"NAK timeout on TX%d ep\n", epnum);  in musb_host_tx()
1322 				"TX end=%d device not responding\n", epnum);  in musb_host_tx()
1331 			musb_ep_select(mbase, epnum);  in musb_host_tx()
1357 		musb_ep_select(mbase, epnum);  in musb_host_tx()
1368 		dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);  in musb_host_tx()
1541 	musb_ep_select(mbase, epnum);  in musb_host_tx()
1815 void musb_host_rx(struct musb *musb, u8 epnum)  in musb_host_rx()  argument
1818 	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;  in musb_host_rx()
1832 	musb_ep_select(mbase, epnum);  in musb_host_rx()
1847 		dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,  in musb_host_rx()
1856 		epnum, rx_csr, urb->actual_length,  in musb_host_rx()
1862 		dev_dbg(musb->controller, "RX end %d STALL\n", epnum);  in musb_host_rx()
1868 		dev_dbg(musb->controller, "end %d RX proto error\n", epnum);  in musb_host_rx()
1876 			dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);  in musb_host_rx()
1892 			musb_ep_select(mbase, epnum);  in musb_host_rx()
1899 			dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);  in musb_host_rx()
1905 				epnum);  in musb_host_rx()
1925 		ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);  in musb_host_rx()
1949 		dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,  in musb_host_rx()
1953 		musb_ep_select(mbase, epnum);  in musb_host_rx()
1972 				    epnum, done ? "off" : "reset",  in musb_host_rx()
1989 			musb_ep_select(mbase, epnum);  in musb_host_rx()
2000 				epnum, musb_readw(epio, MUSB_RXCOUNT),  in musb_host_rx()
2042 				done = musb_host_packet_rx(musb, urb, epnum,  in musb_host_rx()
2051 						epnum, iso_err);  in musb_host_rx()
2082 	int			best_end, epnum;  in musb_schedule()  local
2108 	for (epnum = 1, hw_ep = musb->endpoints + 1;  in musb_schedule()
2109 			epnum < musb->nr_endpoints;  in musb_schedule()
2110 			epnum++, hw_ep++) {  in musb_schedule()
2139 			hw_ep = musb->endpoints + epnum;  in musb_schedule()
2140 			toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);  in musb_schedule()
2148 			best_end = epnum;  in musb_schedule()
2267 	qh->epnum = usb_endpoint_num(epd);  in musb_urb_enqueue()
2273 	type_reg = (qh->type << 4) | qh->epnum;  in musb_urb_enqueue()
2385 	unsigned		hw_end = ep->epnum;  in musb_cleanup_urb()
2401 				is_in ? 'R' : 'T', ep->epnum,  in musb_cleanup_urb()
2408 	if (ep->epnum && is_in) {  in musb_cleanup_urb()
2416 	} else if (ep->epnum) {  in musb_cleanup_urb()