96 static void cppi_reset_tx(struct cppi_tx_stateram __iomem *tx, u32 ptr)  in cppi_reset_tx()  argument
98 	musb_writel(&tx->tx_head, 0, 0);  in cppi_reset_tx()
99 	musb_writel(&tx->tx_buf, 0, 0);  in cppi_reset_tx()
100 	musb_writel(&tx->tx_current, 0, 0);  in cppi_reset_tx()
101 	musb_writel(&tx->tx_buf_current, 0, 0);  in cppi_reset_tx()
102 	musb_writel(&tx->tx_info, 0, 0);  in cppi_reset_tx()
103 	musb_writel(&tx->tx_rem_len, 0, 0);  in cppi_reset_tx()
105 	musb_writel(&tx->tx_complete, 0, ptr);  in cppi_reset_tx()
159 	for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {  in cppi_controller_start()
160 		controller->tx[i].transmit = true;  in cppi_controller_start()
161 		controller->tx[i].index = i;  in cppi_controller_start()
169 	for (i = 0; i < ARRAY_SIZE(controller->tx); i++)  in cppi_controller_start()
170 		cppi_pool_init(controller, controller->tx + i);  in cppi_controller_start()
178 	for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {  in cppi_controller_start()
179 		struct cppi_channel	*tx_ch = controller->tx + i;  in cppi_controller_start()
180 		struct cppi_tx_stateram __iomem *tx;  in cppi_controller_start()  local
184 		tx = tibase + DAVINCI_TXCPPI_STATERAM_OFFSET(i);  in cppi_controller_start()
185 		tx_ch->state_ram = tx;  in cppi_controller_start()
186 		cppi_reset_tx(tx, 0);  in cppi_controller_start()
236 	for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {  in cppi_controller_stop()
238 		controller->tx[i].last_processed = NULL;  in cppi_controller_stop()
239 		cppi_pool_free(controller->tx + i);  in cppi_controller_stop()
299 		if (index >= ARRAY_SIZE(controller->tx)) {  in cppi_channel_allocate()
303 		cppi_ch = controller->tx + index;  in cppi_channel_allocate()
384 	struct cppi_tx_stateram __iomem	*tx = c->state_ram;  in cppi_dump_tx()  local
396 		musb_readl(&tx->tx_head, 0),  in cppi_dump_tx()
397 		musb_readl(&tx->tx_buf, 0),  in cppi_dump_tx()
398 		musb_readl(&tx->tx_current, 0),  in cppi_dump_tx()
399 		musb_readl(&tx->tx_buf_current, 0),  in cppi_dump_tx()
401 		musb_readl(&tx->tx_info, 0),  in cppi_dump_tx()
402 		musb_readl(&tx->tx_rem_len, 0),  in cppi_dump_tx()
404 		musb_readl(&tx->tx_complete, 0)  in cppi_dump_tx()
561 cppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx)  in cppi_next_tx_segment()  argument
563 	unsigned		maxpacket = tx->maxpacket;  in cppi_next_tx_segment()
564 	dma_addr_t		addr = tx->buf_dma + tx->offset;  in cppi_next_tx_segment()
565 	size_t			length = tx->buf_len - tx->offset;  in cppi_next_tx_segment()
569 	struct cppi_tx_stateram	__iomem *tx_ram = tx->state_ram;  in cppi_next_tx_segment()
594 			tx->index,  in cppi_next_tx_segment()
600 	cppi_rndis_update(tx, 0, musb->ctrl_base, rndis);  in cppi_next_tx_segment()
608 	bd = tx->freelist;  in cppi_next_tx_segment()
609 	tx->head = bd;  in cppi_next_tx_segment()
610 	tx->last_processed = NULL;  in cppi_next_tx_segment()
626 		bd->hw_bufp = tx->buf_dma + tx->offset;  in cppi_next_tx_segment()
631 		if ((tx->offset + maxpacket) <= tx->buf_len) {  in cppi_next_tx_segment()
632 			tx->offset += maxpacket;  in cppi_next_tx_segment()
640 			partial_len = tx->buf_len - tx->offset;  in cppi_next_tx_segment()
641 			tx->offset = tx->buf_len;  in cppi_next_tx_segment()
655 		tx->tail = bd;  in cppi_next_tx_segment()
663 	musb_writel(&tx_ram->tx_head, 0, (u32)tx->freelist->dma);  in cppi_next_tx_segment()
665 	cppi_dump_tx(5, tx, "/S");  in cppi_next_tx_segment()
1148 	u32			rx, tx;  in cppi_interrupt()  local
1158 	tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);  in cppi_interrupt()
1161 	if (!tx && !rx) {  in cppi_interrupt()
1167 	dev_dbg(musb->controller, "CPPI IRQ Tx%x Rx%x\n", tx, rx);  in cppi_interrupt()
1170 	for (index = 0; tx; tx = tx >> 1, index++) {  in cppi_interrupt()
1176 		if (!(tx & 1))  in cppi_interrupt()
1179 		tx_ch = cppi->tx + index;  in cppi_interrupt()