155 	void __iomem	*tibase;  in cppi_controller_start()  local
174 	tibase =  controller->tibase;  in cppi_controller_start()
184 		tx = tibase + DAVINCI_TXCPPI_STATERAM_OFFSET(i);  in cppi_controller_start()
194 		rx = tibase + DAVINCI_RXCPPI_STATERAM_OFFSET(i);  in cppi_controller_start()
200 	musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG,  in cppi_controller_start()
202 	musb_writel(tibase, DAVINCI_RXCPPI_INTENAB_REG,  in cppi_controller_start()
206 	musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);  in cppi_controller_start()
207 	musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);  in cppi_controller_start()
210 	musb_writel(tibase, DAVINCI_RNDIS_REG, 0);  in cppi_controller_start()
211 	musb_writel(tibase, DAVINCI_AUTOREQ_REG, 0);  in cppi_controller_start()
222 	void __iomem		*tibase;  in cppi_controller_stop()  local
228 	tibase = controller->tibase;  in cppi_controller_stop()
230 	musb_writel(tibase, DAVINCI_TXCPPI_INTCLR_REG,  in cppi_controller_stop()
232 	musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,  in cppi_controller_stop()
249 	musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);  in cppi_controller_stop()
250 	musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);  in cppi_controller_stop()
261 static inline void core_rxirq_disable(void __iomem *tibase, unsigned epnum)  in core_rxirq_disable()  argument
263 	musb_writel(tibase, DAVINCI_USB_INT_MASK_CLR_REG, 1 << (epnum + 8));  in core_rxirq_disable()
266 static inline void core_rxirq_enable(void __iomem *tibase, unsigned epnum)  in core_rxirq_enable()  argument
268 	musb_writel(tibase, DAVINCI_USB_INT_MASK_SET_REG, 1 << (epnum + 8));  in core_rxirq_enable()
285 	void __iomem		*tibase;  in cppi_channel_allocate()  local
289 	tibase = controller->tibase;  in cppi_channel_allocate()
310 		core_rxirq_disable(tibase, ep->epnum);  in cppi_channel_allocate()
331 	void __iomem		*tibase;  in cppi_channel_release()  local
336 	tibase = c->controller->tibase;  in cppi_channel_release()
341 		core_rxirq_enable(tibase, c->index + 1);  in cppi_channel_release()
363 		musb_readl(c->controller->tibase,  in cppi_dump_rx()
411 		void __iomem *tibase, int is_rndis)  in cppi_rndis_update()  argument
415 		u32	value = musb_readl(tibase, DAVINCI_RNDIS_REG);  in cppi_rndis_update()
424 		musb_writel(tibase, DAVINCI_RNDIS_REG, value);  in cppi_rndis_update()
454 		void __iomem *tibase, int onepacket, unsigned n_bds)  in cppi_autoreq_update()  argument
463 	tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG);  in cppi_autoreq_update()
484 		musb_writel(tibase, DAVINCI_AUTOREQ_REG, val);  in cppi_autoreq_update()
486 			tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG);  in cppi_autoreq_update()
769 	void __iomem		*tibase = musb->ctrl_base;  in cppi_next_rx_segment()  local
810 		n_bds = cppi_autoreq_update(rx, tibase, onepacket, n_bds);  in cppi_next_rx_segment()
823 			musb_readl(tibase,  in cppi_next_rx_segment()
896 	core_rxirq_enable(tibase, rx->index + 1);  in cppi_next_rx_segment()
910 	i = musb_readl(tibase,  in cppi_next_rx_segment()
915 		musb_writel(tibase,  in cppi_next_rx_segment()
919 		musb_writel(tibase,  in cppi_next_rx_segment()
923 	i = musb_readl(tibase,  in cppi_next_rx_segment()
929 		musb_writel(tibase,  in cppi_next_rx_segment()
1146 	void __iomem		*tibase;  in cppi_interrupt()  local
1156 	tibase = musb->ctrl_base;  in cppi_interrupt()
1158 	tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);  in cppi_interrupt()
1159 	rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);  in cppi_interrupt()
1284 			core_rxirq_disable(tibase, index + 1);  in cppi_interrupt()
1290 	musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0);  in cppi_interrupt()
1313 	controller->tibase = mregs - DAVINCI_BASE_OFFSET;  in cppi_dma_controller_create()
1378 	void __iomem		*tibase;  in cppi_channel_abort()  local
1406 	tibase = controller->tibase;  in cppi_channel_abort()
1426 			value = musb_readl(tibase, DAVINCI_TXCPPI_TEAR_REG);  in cppi_channel_abort()
1428 		musb_writel(tibase, DAVINCI_TXCPPI_TEAR_REG, cppi_ch->index);  in cppi_channel_abort()
1470 		core_rxirq_disable(tibase, cppi_ch->index + 1);  in cppi_channel_abort()
1474 			value = musb_readl(tibase, DAVINCI_AUTOREQ_REG);  in cppi_channel_abort()
1476 			musb_writel(tibase, DAVINCI_AUTOREQ_REG, value);  in cppi_channel_abort()