Lines Matching refs:temp
67 u32 temp; in xhci_create_usb3_bos_desc() local
94 temp = readl(&xhci->cap_regs->hcc_params); in xhci_create_usb3_bos_desc()
95 if (HCC_LTC(temp)) in xhci_create_usb3_bos_desc()
100 temp = readl(&xhci->cap_regs->hcs_params3); in xhci_create_usb3_bos_desc()
101 buf[12] = HCS_U1_LATENCY(temp); in xhci_create_usb3_bos_desc()
102 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); in xhci_create_usb3_bos_desc()
157 u16 temp; in xhci_common_hub_descriptor() local
163 temp = 0; in xhci_common_hub_descriptor()
166 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
168 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
171 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
174 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
182 u16 temp; in xhci_usb2_hub_descriptor() local
191 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
192 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
525 u32 temp; in xhci_set_link_state() local
527 temp = readl(port_array[port_id]); in xhci_set_link_state()
528 temp = xhci_port_state_to_neutral(temp); in xhci_set_link_state()
529 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
530 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
531 writel(temp, port_array[port_id]); in xhci_set_link_state()
537 u32 temp; in xhci_set_remote_wake_mask() local
539 temp = readl(port_array[port_id]); in xhci_set_remote_wake_mask()
540 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
543 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
545 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
548 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
550 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
553 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
555 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
557 writel(temp, port_array[port_id]); in xhci_set_remote_wake_mask()
564 u32 temp; in xhci_test_and_clear_bit() local
566 temp = readl(port_array[port_id]); in xhci_test_and_clear_bit()
567 if (temp & port_bit) { in xhci_test_and_clear_bit()
568 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
569 temp |= port_bit; in xhci_test_and_clear_bit()
570 writel(temp, port_array[port_id]); in xhci_test_and_clear_bit()
869 u32 temp, status; in xhci_hub_control() local
916 temp = readl(port_array[wIndex]); in xhci_hub_control()
917 if (temp == 0xffffffff) { in xhci_hub_control()
922 wIndex, temp, flags); in xhci_hub_control()
927 wIndex, temp); in xhci_hub_control()
941 status = xhci_get_ext_port_status(temp, port_li); in xhci_hub_control()
956 temp = readl(port_array[wIndex]); in xhci_hub_control()
957 if (temp == 0xffffffff) { in xhci_hub_control()
961 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
965 temp = readl(port_array[wIndex]); in xhci_hub_control()
966 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
978 temp = readl(port_array[wIndex]); in xhci_hub_control()
979 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
980 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
1003 temp = readl(port_array[wIndex]); in xhci_hub_control()
1007 temp = readl(port_array[wIndex]); in xhci_hub_control()
1012 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1017 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
1020 writel(temp | PORT_PE, port_array[wIndex]); in xhci_hub_control()
1021 temp = readl(port_array[wIndex]); in xhci_hub_control()
1030 temp = readl(port_array[wIndex]); in xhci_hub_control()
1038 if ((temp & PORT_PE) == 0 || in xhci_hub_control()
1064 temp = readl(port_array[wIndex]); in xhci_hub_control()
1075 writel(temp | PORT_POWER, port_array[wIndex]); in xhci_hub_control()
1077 temp = readl(port_array[wIndex]); in xhci_hub_control()
1078 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); in xhci_hub_control()
1081 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_hub_control()
1083 if (temp) in xhci_hub_control()
1089 temp = (temp | PORT_RESET); in xhci_hub_control()
1090 writel(temp, port_array[wIndex]); in xhci_hub_control()
1092 temp = readl(port_array[wIndex]); in xhci_hub_control()
1093 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); in xhci_hub_control()
1098 temp = readl(port_array[wIndex]); in xhci_hub_control()
1101 wIndex, temp); in xhci_hub_control()
1104 temp |= PORT_WR; in xhci_hub_control()
1105 writel(temp, port_array[wIndex]); in xhci_hub_control()
1107 temp = readl(port_array[wIndex]); in xhci_hub_control()
1112 temp = readl(port_array[wIndex] + PORTPMSC); in xhci_hub_control()
1113 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
1114 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
1115 writel(temp, port_array[wIndex] + PORTPMSC); in xhci_hub_control()
1120 temp = readl(port_array[wIndex] + PORTPMSC); in xhci_hub_control()
1121 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
1122 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
1123 writel(temp, port_array[wIndex] + PORTPMSC); in xhci_hub_control()
1129 temp = readl(port_array[wIndex]); in xhci_hub_control()
1135 temp = readl(port_array[wIndex]); in xhci_hub_control()
1136 if (temp == 0xffffffff) { in xhci_hub_control()
1141 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1144 temp = readl(port_array[wIndex]); in xhci_hub_control()
1146 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
1147 if (temp & PORT_RESET) in xhci_hub_control()
1149 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
1150 if ((temp & PORT_PE) == 0) in xhci_hub_control()
1183 port_array[wIndex], temp); in xhci_hub_control()
1187 port_array[wIndex], temp); in xhci_hub_control()
1190 writel(temp & ~PORT_POWER, port_array[wIndex]); in xhci_hub_control()
1193 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_hub_control()
1195 if (temp) in xhci_hub_control()
1224 u32 temp, status; in xhci_hub_status_data() local
1251 temp = readl(port_array[i]); in xhci_hub_status_data()
1252 if (temp == 0xffffffff) { in xhci_hub_status_data()
1256 if ((temp & mask) != 0 || in xhci_hub_status_data()
1263 if ((temp & PORT_RC)) in xhci_hub_status_data()
1352 u32 temp; in xhci_bus_resume() local
1372 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1373 temp &= ~CMD_EIE; in xhci_bus_resume()
1374 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1380 u32 temp; in xhci_bus_resume() local
1382 temp = readl(port_array[port_index]); in xhci_bus_resume()
1383 if (DEV_SUPERSPEED_ANY(temp)) in xhci_bus_resume()
1384 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); in xhci_bus_resume()
1386 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); in xhci_bus_resume()
1388 (temp & PORT_PLS_MASK)) { in xhci_bus_resume()
1390 if (!DEV_SUPERSPEED_ANY(temp)) { in xhci_bus_resume()
1396 writel(temp, port_array[port_index]); in xhci_bus_resume()
1434 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1435 temp |= CMD_EIE; in xhci_bus_resume()
1436 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1437 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()